dts/mediatek/mt6795.dtsi

29 		#size-cells = <0>;
31 		cpu0: cpu@0 {
35 			reg = <0x000>;
44 			reg = <0x001>;
59 			reg = <0x002>;
74 			reg = <0x003>;
89 			reg = <0x100>;
104 			reg = <0x101>;
119 			reg = <0x102>;
134 			reg = <0x103>;
204 		#clock-cells = <0>;
211 		#clock-cells = <0>;
219 		#clock-cells = <0>;
252 			reg = <0 0x10000000 0 0x1000>;
258 			reg = <0 0x10001000 0 0x1000>;
265 			reg = <0 0x10003000 0 0x1000>;
272 			reg = <0 0x10006000 0 0x1000>;
279 				#size-cells = <0>;
287 					#power-domain-cells = <0>;
294 					#power-domain-cells = <0>;
300 					#power-domain-cells = <0>;
307 					#power-domain-cells = <0>;
316 					#power-domain-cells = <0>;
321 					#power-domain-cells = <0>;
329 					#size-cells = <0>;
335 						#size-cells = <0>;
340 							#power-domain-cells = <0>;
350 			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
356 			gpio-ranges = <&pio 0 0 196>;
363 			reg = <0 0x10007000 0 0x100>;
372 			reg = <0 0x10008000 0 0x1000>;
379 			reg = <0 0x1000d000 0 0x1000>;
394 			reg = <0 0x10200620 0 0x20>;
399 			reg = <0 0x10200670 0 0x10>;
407 			reg = <0 0x10205000 0 0x1000>;
418 			reg = <0 0x10209000 0 0x1000>;
424 			reg = <0 0x10209f00 0 0x100>;
430 			reg = <0 0x10212000 0 0x1000>;
442 			reg = <0 0x10221000 0 0x1000>,
443 			      <0 0x10222000 0 0x2000>,
444 			      <0 0x10224000 0 0x2000>,
445 			      <0 0x10226000 0 0x2000>;
454 			reg = <0 0x10390000 0 0x1000>;
455 			ranges = <0 0 0x10390000 0x10000>;
460 				reg = <0x1000 0x1000>;
466 				reg = <0x4000 0x1000>;
472 				reg = <0x5000 0x1000>;
477 				reg = <0x9000 0x5000>;
489 			reg = <0 0x11002000 0 0x400>;
493 			dmas = <&apdma 0>, <&apdma 1>;
501 			reg = <0 0x11003000 0 0x400>;
513 			reg = <0 0x11000380 0 0x60>,
514 			      <0 0x11000400 0 0x60>,
515 			      <0 0x11000480 0 0x60>,
516 			      <0 0x11000500 0 0x60>,
517 			      <0 0x11000580 0 0x60>,
518 			      <0 0x11000600 0 0x60>,
519 			      <0 0x11000680 0 0x60>,
520 			      <0 0x11000700 0 0x60>;
539 			reg = <0 0x11004000 0 0x400>;
551 			reg = <0 0x11005000 0 0x400>;
562 			reg = <0 0x11006000 0 0x1000>;
581 			reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
587 			#size-cells = <0>;
593 			reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
599 			#size-cells = <0>;
605 			reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
611 			#size-cells = <0>;
617 			reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
623 			#size-cells = <0>;
629 			reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
635 			#size-cells = <0>;
641 			reg = <0 0x11230000 0 0x1000>;
652 			reg = <0 0x11240000 0 0x1000>;
662 			reg = <0 0x11250000 0 0x1000>;
672 			reg = <0 0x11260000 0 0x1000>;
682 			reg = <0 0x14000000 0 0x1000>;
688 			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
690 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
695 			reg = <0 0x14021000 0 0x1000>;
699 			mediatek,larb-id = <0>;
705 			reg = <0 0x14022000 0 0x1000>;
713 			reg = <0 0x15001000 0 0x1000>;
723 			reg = <0 0x16000000 0 0x1000>;
729 			reg = <0 0x16010000 0 0x1000>;
739 			reg = <0 0x18000000 0 0x1000>;
745 			reg = <0 0x18001000 0 0x1000>;