Lines Matching +full:0 +full:x46000000
27 reg = <0 0x40000000 0 0x1e800000>;
37 reg = <0 0x43000000 0 0x30000>;
43 reg = <0 0x44800000 0 0x100000>;
48 reg = <0 0x46000000 0 0x400000>;
63 pinctrl-0 = <&i2c0_pins>;
69 pinctrl-0 = <&i2c1_pins>;
74 reg = <0x10>;
76 pinctrl-0 = <&accel_pins>;
81 reg = <0x12>;
87 pinctrl-0 = <&i2c2_pins>;
92 reg = <0x20>;
94 #size-cells = <0>;
97 pinctrl-0 = <&ts_pins>;
102 reg = <0x1>;
107 reg = <0x12>;
115 pinctrl-0 = <&i2c3_pins>;
120 reg = <0x28>;
123 pinctrl-0 = <&nfc_pins>;
130 reg = <0x48>;
133 pinctrl-0 = <&proximity_pins>;
139 mediatek,latch-ck = <0x14>; /* hs400 */
142 mediatek,hs400-ds-dly3 = <0x1a>;
145 pinctrl-0 = <&mmc0_pins_default>;
347 pinctrl-0 = <&uart0_pins>;
354 pinctrl-0 = <&uart2_pins>;