dts/marvell/cn9130-crb.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 		stdout-path = "serial0:115200n8";
30 		compatible = "regulator-gpio";
31 		regulator-name = "ap0_mmc_vccq";
32 		regulator-min-microvolt = <1800000>;
33 		regulator-max-microvolt = <3300000>;
34 		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
40 		compatible = "regulator-fixed";
41 		regulator-name = "cp0-xhci1-vbus";
42 		regulator-min-microvolt = <5000000>;
43 		regulator-max-microvolt = <5000000>;
44 		enable-active-high;
49 		compatible = "usb-nop-xceiv";
53 		compatible = "usb-nop-xceiv";
54 		vcc-supply = <&cp0_reg_usb3_vbus1>;
58 		compatible = "regulator-gpio";
59 		regulator-name = "cp0_sd_vccq";
60 		regulator-min-microvolt = <1800000>;
61 		regulator-max-microvolt = <3300000>;
62 		gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
68 		compatible = "regulator-fixed";
69 		regulator-name = "cp0_sd_vcc";
70 		regulator-min-microvolt = <3300000>;
71 		regulator-max-microvolt = <3300000>;
73 		enable-active-high;
74 		regulator-always-on;
79 		i2c-bus = <&cp0_i2c1>;
80 		mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
81 		los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
82 		tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
83 		tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
84 		maximum-power-milliwatt = <3000>;
93 /* on-board eMMC U6 */
95 	pinctrl-names = "default";
96 	bus-width = <8>;
98 	mmc-ddr-1_8v;
99 	vqmmc-supply = <&ap0_reg_mmc_vccq>;
104 		compatible = "marvell,cp115-standalone-pinctrl";
106 		cp0_i2c0_pins: cp0-i2c-pins-0 {
110 		cp0_i2c1_pins: cp0-i2c-pins-1 {
114 		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
118 		cp0_sdhci_pins: cp0-sdhi-pins-0 {
123 		cp0_spi1_pins: cp0-spi-pins-1 {
139 	pinctrl-names = "default";
140 	pinctrl-0 = <&cp0_i2c0_pins>;
142 	clock-frequency = <100000>;
145 		gpio-controller;
146 		#gpio-cells = <2>;
153 	pinctrl-names = "default";
154 	pinctrl-0 = <&cp0_i2c1_pins>;
155 	clock-frequency = <100000>;
161 	pinctrl-names = "default";
162 	pinctrl-0 = <&cp0_sdhci_pins
164 	bus-width = <4>;
165 	cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
166 	vqmmc-supply = <&cp0_reg_sd_vccq>;
167 	vmmc-supply = <&cp0_reg_sd_vcc>;
172 	pinctrl-names = "default";
173 	pinctrl-0 = <&cp0_spi1_pins>;
179 		#address-cells = <0x1>;
180 		#size-cells = <0x1>;
181 		compatible = "jedec,spi-nor";
183 		/* On-board MUX does not allow higher frequencies */
184 		spi-max-frequency = <40000000>;
187 			compatible = "fixed-partitions";
188 			#address-cells = <1>;
189 			#size-cells = <1>;
192 				label = "U-Boot";
206 	phy0: ethernet-phy@0 {
213 		#address-cells = <1>;
214 		#size-cells = <0>;
216 		interrupt-parent = <&cp0_gpio1>;
218 		interrupt-controller;
219 		#interrupt-cells = <2>;
224 			#address-cells = <1>;
225 			#size-cells = <0>;
230 				phy-handle = <&switch0phy1>;
236 				phy-handle = <&switch0phy2>;
242 				phy-handle = <&switch0phy3>;
248 				phy-handle = <&switch0phy4>;
254 				phy-handle = <&switch0phy5>;
260 				phy-handle = <&switch0phy6>;
266 				phy-handle = <&switch0phy7>;
272 				phy-handle = <&switch0phy8>;
278 				phy-mode = "10gbase-r";
280 				managed = "in-band-status";
286 				phy-mode = "10gbase-r";
287 				managed = "in-band-status";
293 			#address-cells = <1>;
294 			#size-cells = <0>;
333 	nbaset_phy0: ethernet-phy@0 {
334 		compatible = "ethernet-phy-ieee802.3-c45";
346 	phy-mode = "10gbase-r";
347 	managed = "in-band-status";
354 	phy-mode = "rgmii-id";
358 	/* This port uses "2500base-t" phy-mode */