Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
87 reg = <0x20000>;
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
95 reg = <0x20001>;
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
103 reg = <0x20002>;
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
111 reg = <0x20003>;
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
119 reg = <0x20100>;
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
127 reg = <0x20101>;
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
135 reg = <0x20102>;
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
143 reg = <0x20103>;
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
151 reg = <0x20200>;
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
159 reg = <0x20201>;
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
167 reg = <0x20202>;
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
175 reg = <0x20203>;
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
183 reg = <0x20300>;
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
191 reg = <0x20301>;
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
199 reg = <0x20302>;
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
207 reg = <0x20303>;
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
213 compatible = "cache";
214 cache-level = <2>;
215 cache-unified;
218 cluster1_l2: l2-cache1 {
219 compatible = "cache";
220 cache-level = <2>;
221 cache-unified;
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
226 cache-level = <2>;
227 cache-unified;
230 cluster3_l2: l2-cache3 {
231 compatible = "cache";
232 cache-level = <2>;
233 cache-unified;
237 gic: interrupt-controller@8d000000 {
238 compatible = "arm,gic-v3";
239 #interrupt-cells = <3>;
240 #address-cells = <2>;
241 #size-cells = <2>;
243 interrupt-controller;
244 #redistributor-regions = <1>;
245 redistributor-stride = <0x0 0x30000>;
246 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
247 <0x0 0x8d100000 0 0x300000>, /* GICR */
248 <0x0 0xfe000000 0 0x10000>, /* GICC */
249 <0x0 0xfe010000 0 0x10000>, /* GICH */
250 <0x0 0xfe020000 0 0x10000>; /* GICV */
253 its_peri: msi-controller@8c000000 {
254 compatible = "arm,gic-v3-its";
255 msi-controller;
256 #msi-cells = <1>;
257 reg = <0x0 0x8c000000 0x0 0x40000>;
260 its_m3: msi-controller@a3000000 {
261 compatible = "arm,gic-v3-its";
262 msi-controller;
263 #msi-cells = <1>;
264 reg = <0x0 0xa3000000 0x0 0x40000>;
267 its_pcie: msi-controller@b7000000 {
268 compatible = "arm,gic-v3-its";
269 msi-controller;
270 #msi-cells = <1>;
271 reg = <0x0 0xb7000000 0x0 0x40000>;
274 its_dsa: msi-controller@c6000000 {
275 compatible = "arm,gic-v3-its";
276 msi-controller;
277 #msi-cells = <1>;
278 reg = <0x0 0xc6000000 0x0 0x40000>;
283 compatible = "arm,armv8-timer";
291 compatible = "arm,cortex-a57-pmu";
296 compatible = "simple-bus";
297 #address-cells = <2>;
298 #size-cells = <2>;
302 compatible = "fixed-clock";
303 #clock-cells = <0>;
304 clock-frequency = <200000000>;
308 compatible = "snps,dw-apb-uart";
309 reg = <0x0 0x80300000 0x0 0x10000>;
312 clock-names = "baudclk", "apb_pclk";
313 reg-shift = <2>;
314 reg-io-width = <4>;
319 compatible = "snps,dw-apb-uart";
320 reg = <0x0 0x80310000 0x0 0x10000>;
323 clock-names = "baudclk", "apb_pclk";
324 reg-shift = <2>;
325 reg-io-width = <4>;
329 lbc: local-bus@80380000 {
330 compatible = "hisilicon,hisi-localbus", "simple-bus";
331 reg = <0x0 0x80380000 0x0 0x10000>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "snps,dw-apb-gpio";
339 reg = <0x0 0x802e0000 0x0 0x10000>;
342 porta: gpio-controller@0 {
343 compatible = "snps,dw-apb-gpio-port";
344 gpio-controller;
345 #gpio-cells = <2>;
347 reg = <0>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "snps,dw-apb-gpio";
358 reg = <0x0 0x802f0000 0x0 0x10000>;
361 portb: gpio-controller@0 {
362 compatible = "snps,dw-apb-gpio-port";
363 gpio-controller;
364 #gpio-cells = <2>;
366 reg = <0>;
367 interrupt-controller;
368 #interrupt-cells = <2>;