dts/hisilicon/hi3798cv200.dtsi

85 		crg: clock-reset-controller@8a22000 {  label
86 			compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
119 				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
120 				resets = <&crg 0xbc 4>;
127 					resets = <&crg 0xbc 8>;
133 					resets = <&crg 0xbc 9>;
140 				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
141 				resets = <&crg 0xbc 6>;
148 					resets = <&crg 0xbc 10>;
156 				clocks = <&crg HISTB_COMBPHY0_CLK>;
157 				resets = <&crg 0x188 4>;
158 				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
167 				clocks = <&crg HISTB_COMBPHY1_CLK>;
168 				resets = <&crg 0x188 12>;
169 				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
228 			clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
240 			clocks = <&crg HISTB_I2C0_CLK>;
251 			clocks = <&crg HISTB_I2C1_CLK>;
262 			clocks = <&crg HISTB_I2C2_CLK>;
273 			clocks = <&crg HISTB_I2C3_CLK>;
284 			clocks = <&crg HISTB_I2C4_CLK>;
294 			clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
305 			clocks = <&crg HISTB_SDIO0_BIU_CLK>,
306 				 <&crg HISTB_SDIO0_CIU_CLK>;
308 			resets = <&crg 0x9c 4>;
317 			clocks = <&crg HISTB_MMC_CIU_CLK>,
318 				 <&crg HISTB_MMC_BIU_CLK>,
319 				 <&crg HISTB_MMC_SAMPLE_CLK>,
320 				 <&crg HISTB_MMC_DRV_CLK>;
322 			resets = <&crg 0xa0 4>;
336 			clocks = <&crg HISTB_APB_CLK>;
356 			clocks = <&crg HISTB_APB_CLK>;
370 			clocks = <&crg HISTB_APB_CLK>;
389 			clocks = <&crg HISTB_APB_CLK>;
403 			clocks = <&crg HISTB_APB_CLK>;
416 			clocks = <&crg HISTB_APB_CLK>;
430 			clocks = <&crg HISTB_APB_CLK>;
444 			clocks = <&crg HISTB_APB_CLK>;
458 			clocks = <&crg HISTB_APB_CLK>;
472 			clocks = <&crg HISTB_APB_CLK>;
486 			clocks = <&crg HISTB_APB_CLK>;
500 			clocks = <&crg HISTB_APB_CLK>;
514 			clocks = <&crg HISTB_APB_CLK>;
524 			clocks = <&crg HISTB_ETH0_MAC_CLK>,
525 				 <&crg HISTB_ETH0_MACIF_CLK>;
527 			resets = <&crg 0xcc 8>,
528 				 <&crg 0xcc 10>,
539 			clocks = <&crg HISTB_ETH1_MAC_CLK>,
540 				 <&crg HISTB_ETH1_MACIF_CLK>;
542 			resets = <&crg 0xcc 9>,
543 				 <&crg 0xcc 11>,
575 			clocks = <&crg HISTB_PCIE_AUX_CLK>,
576 				 <&crg HISTB_PCIE_PIPE_CLK>,
577 				 <&crg HISTB_PCIE_SYS_CLK>,
578 				 <&crg HISTB_PCIE_BUS_CLK>;
580 			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
591 			clocks = <&crg HISTB_USB2_BUS_CLK>,
592 				 <&crg HISTB_USB2_12M_CLK>,
593 				 <&crg HISTB_USB2_48M_CLK>;
595 			resets = <&crg 0xb8 12>;
606 			clocks = <&crg HISTB_USB2_BUS_CLK>,
607 				 <&crg HISTB_USB2_PHY_CLK>,
608 				 <&crg HISTB_USB2_UTMI_CLK>;
610 			resets = <&crg 0xb8 12>,
611 				 <&crg 0xb8 16>,
612 				 <&crg 0xb8 13>;