Lines Matching +full:0 +full:x44450000
48 #size-cells = <0>;
55 arm,psci-suspend-param = <0x0010033>;
64 A55_0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x100>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
100 #clock-cells = <0>;
128 reg = <0 0x48000000 0 0x10000>,
129 <0 0x48040000 0 0xc0000>;
141 thermal-sensors = <&tmu 0>;
174 soc@0 {
178 ranges = <0x0 0x0 0x0 0x80000000>,
179 <0x28000000 0x0 0x28000000 0x10000000>;
183 reg = <0x44000000 0x800000>;
190 reg = <0x44210000 0x1000>;
195 reg = <0x44230000 0x10000>;
204 reg = <0x44290000 0x30000>;
213 reg = <0x442d0000 0x10000>;
222 reg = <0x442e0000 0x10000>;
231 reg = <0x44310000 0x1000>;
239 reg = <0x44320000 0x10000>;
247 reg = <0x44340000 0x10000>;
249 #size-cells = <0>;
259 reg = <0x44350000 0x10000>;
261 #size-cells = <0>;
271 #size-cells = <0>;
273 reg = <0x44360000 0x10000>;
283 #size-cells = <0>;
285 reg = <0x44370000 0x10000>;
295 reg = <0x44380000 0x1000>;
304 reg = <0x44390000 0x1000>;
313 reg = <0x443a0000 0x10000>;
321 fsl,clk-source = /bits/ 8 <0>;
322 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
328 reg = <0x443c0000 0x10000>;
334 reg = <0x44440000 0x10000>;
350 reg = <0x44450000 0x10000>;
359 reg = <0x44460000 0x10000>;
366 reg = <0x44461800 0x400>, <0x44464800 0x400>;
367 #power-domain-cells = <0>;
374 reg = <0x44462400 0x400>, <0x44465800 0x400>;
375 #power-domain-cells = <0>;
383 reg = <0x44480000 0x2000>;
388 reg = <0x44482000 0x1000>;
391 fsl,tmu-range = <0x800000da 0x800000e9
392 0x80000102 0x8000012a
393 0x80000166 0x800001a7
394 0x800001b6>;
395 fsl,tmu-calibration = <0x00000000 0x0000000e
396 0x00000001 0x00000029
397 0x00000002 0x00000056
398 0x00000003 0x000000a2
399 0x00000004 0x00000116
400 0x00000005 0x00000195
401 0x00000006 0x000001b2>;
408 reg = <0x44530000 0x10000>;
422 reg = <0x42000000 0x800000>;
429 reg = <0x42420000 0x1000>;
434 reg = <0x42440000 0x10000>;
443 reg = <0x42490000 0x10000>;
452 reg = <0x424a0000 0x10000>;
461 reg = <0x424b0000 0x10000>;
470 reg = <0x424e0000 0x1000>;
478 reg = <0x424f0000 0x10000>;
486 reg = <0x42500000 0x10000>;
494 reg = <0x42510000 0x10000>;
502 reg = <0x42530000 0x10000>;
504 #size-cells = <0>;
514 reg = <0x42540000 0x10000>;
516 #size-cells = <0>;
526 #size-cells = <0>;
528 reg = <0x42550000 0x10000>;
538 #size-cells = <0>;
540 reg = <0x42560000 0x10000>;
550 reg = <0x42570000 0x1000>;
559 reg = <0x42580000 0x1000>;
568 reg = <0x42590000 0x1000>;
577 reg = <0x425a0000 0x1000>;
586 reg = <0x425b0000 0x10000>;
594 fsl,clk-source = /bits/ 8 <0>;
595 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
601 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
604 #size-cells = <0>;
616 reg = <0x42690000 0x1000>;
625 reg = <0x426a0000 0x1000>;
634 reg = <0x426b0000 0x10000>;
636 #size-cells = <0>;
646 reg = <0x426c0000 0x10000>;
648 #size-cells = <0>;
658 reg = <0x426d0000 0x10000>;
660 #size-cells = <0>;
670 reg = <0x426e0000 0x10000>;
672 #size-cells = <0>;
682 #size-cells = <0>;
684 reg = <0x426f0000 0x10000>;
694 #size-cells = <0>;
696 reg = <0x42700000 0x10000>;
706 #size-cells = <0>;
708 reg = <0x42710000 0x10000>;
718 #size-cells = <0>;
720 reg = <0x42720000 0x10000>;
732 reg = <0x42800000 0x800000>;
739 reg = <0x42850000 0x10000>;
753 reg = <0x42860000 0x10000>;
767 reg = <0x42890000 0x10000>;
788 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
796 reg = <0x428a0000 0x10000>;
811 intf_mode = <&wakeupmix_gpr 0x28>;
820 reg = <0x428b0000 0x10000>;
835 reg = <0x43810080 0x1000>, <0x43810040 0x40>;
844 gpio-ranges = <&iomuxc 0 4 30>;
849 reg = <0x43820080 0x1000>, <0x43820040 0x40>;
858 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
859 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
864 reg = <0x43830080 0x1000>, <0x43830040 0x40>;
873 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
878 reg = <0x47400080 0x1000>, <0x47400040 0x40>;
887 gpio-ranges = <&iomuxc 0 92 16>;
892 reg = <0x47510000 0x10000>;
897 reg = <0x4ec 0x6>;
901 reg = <0x4f2 0x6>;
908 reg = <0x47520000 0x10000>;
917 reg = <0x4ac10000 0x10000>;
937 reg = <0x4e300dc0 0x200>;