dts/freescale/imx8ulp-evk.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx8ulp.dtsi"
12 	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
15 		stdout-path = &lpuart5;
23 	reserved-memory {
24 		#address-cells = <2>;
25 		#size-cells = <2>;
29 			compatible = "shared-dma-pool";
32 			linux,cma-default;
35 		m33_reserved: noncacheable-section@a8600000 {
37 			no-map;
40 		rsc_table: rsc-table@1fff8000{
42 			no-map;
47 			no-map;
52 			no-map;
57 			no-map;
62 			no-map;
66 			compatible = "shared-dma-pool";
68 			no-map;
72 	clock_ext_rmii: clock-ext-rmii {
73 		compatible = "fixed-clock";
74 		clock-frequency = <50000000>;
75 		clock-output-names = "ext_rmii_clk";
76 		#clock-cells = <0>;
79 	clock_ext_ts: clock-ext-ts {
80 		compatible = "fixed-clock";
82 		clock-frequency = <50000000>;
83 		clock-output-names = "ext_ts_clk";
84 		#clock-cells = <0>;
89 	mbox-names = "tx", "rx", "rxdb";
93 	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
99 	pinctrl-names = "default", "sleep";
100 	pinctrl-0 = <&pinctrl_flexspi2_ptd>;
101 	pinctrl-1 = <&pinctrl_flexspi2_ptd>;
105 		compatible = "jedec,spi-nor";
107 		spi-max-frequency = <200000000>;
108 		spi-tx-bus-width = <8>;
109 		spi-rx-bus-width = <8>;
115 	pinctrl-names = "default", "sleep";
116 	pinctrl-0 = <&pinctrl_lpuart5>;
117 	pinctrl-1 = <&pinctrl_lpuart5>;
122 	#address-cells = <1>;
123 	#size-cells = <0>;
124 	clock-frequency = <400000>;
125 	pinctrl-names = "default", "sleep";
126 	pinctrl-0 = <&pinctrl_lpi2c7>;
127 	pinctrl-1 = <&pinctrl_lpi2c7>;
133 		gpio-controller;
134 		#gpio-cells = <2>;
139 	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
140 	pinctrl-0 = <&pinctrl_usdhc0>;
141 	pinctrl-1 = <&pinctrl_usdhc0>;
142 	pinctrl-2 = <&pinctrl_usdhc0>;
143 	pinctrl-3 = <&pinctrl_usdhc0>;
144 	non-removable;
145 	bus-width = <8>;
150 	pinctrl-names = "default", "sleep";
151 	pinctrl-0 = <&pinctrl_enet>;
152 	pinctrl-1 = <&pinctrl_enet>;
153 	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
155 		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
157 	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
158 	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
159 	assigned-clock-parents = <&clock_ext_ts>;
160 	phy-mode = "rmii";
161 	phy-handle = <&ethphy>;
165 		#address-cells = <1>;
166 		#size-cells = <0>;
168 		ethphy: ethernet-phy@1 {
170 			micrel,led-mode = <1>;