Lines Matching +full:0 +full:x30e20000
48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
98 d-cache-size = <0x8000>;
109 reg = <0x3>;
113 i-cache-size = <0x8000>;
116 d-cache-size = <0x8000>;
128 cache-size = <0x80000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
149 opp-supported-hw = <0xa0>, <0x7>;
157 opp-supported-hw = <0x20>, <0x3>;
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
211 reg = <0 0x92400000 0 0x2000000>;
231 thermal-sensors = <&tmu 0>;
299 soc: soc@0 {
303 ranges = <0x0 0x0 0x0 0x3e000000>;
309 reg = <0x28440000 0x1000>;
325 reg = <0x28540000 0x1000>;
341 reg = <0x28640000 0x1000>;
357 reg = <0x28740000 0x1000>;
380 #size-cells = <0>;
382 port@0 {
383 reg = <0>;
426 reg = <0x28c03000 0x1000>;
432 #size-cells = <0>;
434 port@0 {
435 reg = <0>;
471 reg = <0x28c04000 0x1000>;
494 reg = <0x28c06000 0x1000>;
509 reg = <0x30000000 0x400000>;
516 reg = <0x30200000 0x10000>;
524 gpio-ranges = <&iomuxc 0 5 30>;
529 reg = <0x30210000 0x10000>;
537 gpio-ranges = <&iomuxc 0 35 21>;
542 reg = <0x30220000 0x10000>;
550 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
555 reg = <0x30230000 0x10000>;
563 gpio-ranges = <&iomuxc 0 82 32>;
568 reg = <0x30240000 0x10000>;
576 gpio-ranges = <&iomuxc 0 114 30>;
581 reg = <0x30260000 0x10000>;
590 reg = <0x30280000 0x10000>;
598 reg = <0x30290000 0x10000>;
606 reg = <0x302a0000 0x10000>;
614 reg = <0x302d0000 0x10000>;
622 reg = <0x302e0000 0x10000>;
630 reg = <0x302f0000 0x10000>;
638 reg = <0x30330000 0x10000>;
643 reg = <0x30340000 0x10000>;
648 reg = <0x30350000 0x10000>;
660 * Fuse Address = (ADDR * 4) + 0x400
663 * +0x10 in Fusemap Description Table (e.g.
664 * reg = <0x8 0x8> describes fuses 0x420 and
665 * 0x430).
667 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
668 reg = <0x8 0x8>;
671 cpu_speed_grade: speed-grade@10 { /* 0x440 */
672 reg = <0x10 4>;
675 eth_mac1: mac-address@90 { /* 0x640 */
676 reg = <0x90 6>;
679 eth_mac2: mac-address@96 { /* 0x658 */
680 reg = <0x96 6>;
683 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
684 reg = <0x264 0x10>;
690 reg = <0x30360000 0x10000>;
695 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
696 reg = <0x30370000 0x10000>;
699 compatible = "fsl,sec-v4.0-mon-rtc-lp";
701 offset = <0x34>;
709 compatible = "fsl,sec-v4.0-pwrkey";
727 reg = <0x30380000 0x10000>;
743 assigned-clock-rates = <0>, <0>,
751 reg = <0x30390000 0x10000>;
758 reg = <0x303a0000 0x1000>;
766 #size-cells = <0>;
768 pgc_mipi_phy1: power-domain@0 {
769 #power-domain-cells = <0>;
774 #power-domain-cells = <0>;
779 #power-domain-cells = <0>;
784 #power-domain-cells = <0>;
789 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
819 #power-domain-cells = <0>;
826 #power-domain-cells = <0>;
838 #power-domain-cells = <0>;
844 #power-domain-cells = <0>;
852 #power-domain-cells = <0>;
859 #power-domain-cells = <0>;
866 #power-domain-cells = <0>;
874 #power-domain-cells = <0>;
881 #power-domain-cells = <0>;
893 #power-domain-cells = <0>;
898 #power-domain-cells = <0>;
903 #power-domain-cells = <0>;
913 #power-domain-cells = <0>;
923 reg = <0x30400000 0x400000>;
930 reg = <0x30660000 0x10000>;
941 reg = <0x30670000 0x10000>;
952 reg = <0x30680000 0x10000>;
963 reg = <0x30690000 0x10000>;
974 reg = <0x306a0000 0x20000>;
982 reg = <0x306e0000 0x10000>;
990 reg = <0x306f0000 0x10000>;
998 reg = <0x30700000 0x10000>;
1007 reg = <0x30800000 0x400000>;
1014 reg = <0x30800000 0x100000>;
1021 #size-cells = <0>;
1023 reg = <0x30820000 0x10000>;
1031 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1038 #size-cells = <0>;
1040 reg = <0x30830000 0x10000>;
1055 #size-cells = <0>;
1057 reg = <0x30840000 0x10000>;
1072 reg = <0x30860000 0x10000>;
1077 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1084 reg = <0x30880000 0x10000>;
1089 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1096 reg = <0x30890000 0x10000>;
1101 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1108 reg = <0x308c0000 0x10000>;
1116 fsl,clk-source = /bits/ 8 <0>;
1117 fsl,stop-mode = <&gpr 0x10 4>;
1123 reg = <0x308d0000 0x10000>;
1131 fsl,clk-source = /bits/ 8 <0>;
1132 fsl,stop-mode = <&gpr 0x10 5>;
1138 compatible = "fsl,sec-v4.0";
1141 reg = <0x30900000 0x40000>;
1142 ranges = <0 0x30900000 0x40000>;
1149 compatible = "fsl,sec-v4.0-job-ring";
1150 reg = <0x1000 0x1000>;
1156 compatible = "fsl,sec-v4.0-job-ring";
1157 reg = <0x2000 0x1000>;
1162 compatible = "fsl,sec-v4.0-job-ring";
1163 reg = <0x3000 0x1000>;
1171 #size-cells = <0>;
1172 reg = <0x30a20000 0x10000>;
1181 #size-cells = <0>;
1182 reg = <0x30a30000 0x10000>;
1191 #size-cells = <0>;
1192 reg = <0x30a40000 0x10000>;
1201 #size-cells = <0>;
1202 reg = <0x30a50000 0x10000>;
1210 reg = <0x30a60000 0x10000>;
1215 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1222 reg = <0x30aa0000 0x10000>;
1230 reg = <0x30e60000 0x10000>;
1239 #size-cells = <0>;
1240 reg = <0x30ad0000 0x10000>;
1249 #size-cells = <0>;
1250 reg = <0x30ae0000 0x10000>;
1258 reg = <0x30b40000 0x10000>;
1272 reg = <0x30b50000 0x10000>;
1286 reg = <0x30b60000 0x10000>;
1300 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1309 #size-cells = <0>;
1315 reg = <0x30bd0000 0x10000>;
1326 reg = <0x30be0000 0x10000>;
1346 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,stop-mode = <&gpr 0x10 3>;
1357 reg = <0x30bf0000 0x10000>;
1372 assigned-clock-rates = <0>, <100000000>, <125000000>;
1375 intf_mode = <&gpr 0x4>;
1382 reg = <0x30c00000 0x400000>;
1389 reg = <0x30c00000 0x100000>;
1396 reg = <0x30c10000 0x10000>;
1397 #sound-dai-cells = <0>;
1404 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1412 reg = <0x30c20000 0x10000>;
1413 #sound-dai-cells = <0>;
1420 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1428 reg = <0x30c30000 0x10000>;
1429 #sound-dai-cells = <0>;
1436 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1444 reg = <0x30c50000 0x10000>;
1445 #sound-dai-cells = <0>;
1452 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1460 reg = <0x30c60000 0x10000>;
1461 #sound-dai-cells = <0>;
1468 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1476 reg = <0x30c80000 0x10000>;
1477 #sound-dai-cells = <0>;
1484 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1493 reg = <0x30e00000 0x10000>;
1504 reg = <0x30e10000 0x10000>;
1515 reg = <0x30e20000 0x10000>;
1533 reg = <0x32700000 0x100000>;
1553 reg = <0x32c00000 0x400000>;
1560 reg = <0x32e00000 0x4000>;
1572 #size-cells = <0>;
1574 port@0 {
1575 reg = <0>;
1594 reg = <0x32e30000 0x10000>;
1604 reg = <0x32e40000 0x10000>;
1620 #size-cells = <0>;
1622 port@0 {
1623 reg = <0>;
1638 reg = <0x32e50000 0x10000>;
1654 #size-cells = <0>;
1656 port@0 {
1657 reg = <0>;
1672 reg = <0x32e60000 0x400>;
1688 #size-cells = <0>;
1690 port@0 {
1691 reg = <0>;
1702 reg = <0x32e80000 0x10000>;
1720 reg = <0x32e90000 0x10000>;
1739 reg = <0x32ec0000 0x10000>;
1789 <0>, <0>, <1039500000>;
1794 reg = <0x5c 0x4>, <0x128 0x4>;
1804 #size-cells = <0>;
1806 port@0 {
1807 reg = <0>;
1833 reg = <0x32f00000 0x10000>;
1838 #phy-cells = <0>;
1844 reg = <0x32f10000 0x24>;
1859 #clock-cells = <0>;
1864 reg = <0x32fc0000 0x1000>;
1886 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1898 bus-range = <0x00 0xff>;
1899 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1900 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1906 interrupt-map-mask = <0 0 0 0x7>;
1907 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1908 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1909 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1910 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1912 linux,pci-domain = <0>;
1924 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1950 reg = <0x38000000 0x8000>;
1967 reg = <0x38008000 0x8000>;
1981 reg = <0x38300000 0x10000>;
1992 reg = <0x38310000 0x10000>;
2003 reg = <0x38330000 0x100>;
2023 reg = <0x38500000 0x200000>;
2035 reg = <0x38800000 0x10000>,
2036 <0x38880000 0xc0000>;
2045 reg = <0x3d400000 0x400000>;
2051 reg = <0x3d800000 0x400000>;
2057 reg = <0x381f0040 0x40>;
2063 #phy-cells = <0>;
2069 reg = <0x32f10100 0x8>,
2070 <0x381f0000 0x20>;
2078 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2084 reg = <0x38100000 0x10000>;
2100 reg = <0x382f0040 0x40>;
2106 #phy-cells = <0>;
2112 reg = <0x32f10108 0x8>,
2113 <0x382f0000 0x20>;
2121 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2127 reg = <0x38200000 0x10000>;
2142 reg = <0x3b6e8000 0x88000>;
2145 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2146 <&mu2 3 0>, <&mu2 3 1>;