Lines Matching +full:clk +full:- +full:internal +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/leds/leds-pca9532.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-som.dtsi"
14 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
15 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
16 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
19 stdout-path = &uart1;
22 reg_usdhc2_vmmc: regulator-usdhc2 {
23 compatible = "regulator-fixed";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
26 regulator-name = "VSD_3V3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
30 enable-active-high;
31 startup-delay-us = <100>;
32 off-on-delay-us = <12000>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_eqos>;
39 phy-mode = "rgmii-id";
40 phy-handle = <ðphy0>;
44 compatible = "snps,dwmac-mdio";
45 #address-cells = <1>;
46 #size-cells = <0>;
48 ethphy0: ethernet-phy@1 {
49 compatible = "ethernet-phy-ieee802.3-c22";
51 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
52 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
53 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
54 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
55 enet-phy-lane-no-swap;
61 clock-frequency = <400000>;
62 pinctrl-names = "default", "gpio";
63 pinctrl-0 = <&pinctrl_i2c2>;
64 pinctrl-1 = <&pinctrl_i2c2_gpio>;
65 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
66 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
79 led-1 {
83 led-2 {
87 led-3 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart1>;
104 /* SD-Card */
106 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
107 assigned-clock-rates = <200000000>;
108 pinctrl-names = "default", "state_100mhz", "state_200mhz";
109 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
110 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
111 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
112 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
113 vmmc-supply = <®_usdhc2_vmmc>;
114 bus-width = <4>;
166 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
184 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
196 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {