Lines Matching +full:clk +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include "imx8mm-tqma8mqml.dtsi"
12 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
13 compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
24 reg_usdhc2_vmmc: regulator-vmmc {
25 compatible = "regulator-fixed";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
32 enable-active-high;
33 startup-delay-us = <100>;
34 off-on-delay-us = <12000>;
38 compatible = "gpio-usb-b-connector", "usb-b-connector";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usb1_connector>;
43 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
46 #address-cells = <1>;
47 #size-cells = <0>;
52 remote-endpoint = <&usb1_drd_sw>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 vcc-supply = <®_vcc_3v3>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_expander>;
68 interrupt-parent = <&gpio1>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
81 reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
82 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
83 <&clk IMX8MM_CLK_PCIE1_AUX>;
84 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
85 <&clk IMX8MM_CLK_PCIE1_CTRL>;
86 assigned-clock-rates = <10000000>, <250000000>;
87 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
88 <&clk IMX8MM_SYS_PLL2_250M>;
93 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
94 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
95 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
96 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
97 <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
98 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
99 <&clk IMX8MM_AUDIO_PLL2_OUT>;
103 clock-names = "mclk";
104 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
108 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
109 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
113 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
114 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_usbotg1>;
121 srp-disable;
122 hnp-disable;
123 adp-disable;
124 power-active-high;
125 over-current-active-low;
126 usb-role-switch;
131 remote-endpoint = <&usb_dr_connector>;
138 disable-over-current;
139 vbus-supply = <®_hub_vbus>;
145 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>,
152 fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>,
159 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>;
163 fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>,
180 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>,
186 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>,
191 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>,
196 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>,
201 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>,
206 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>,
211 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>;
215 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>;
219 fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>,
229 fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>,
234 fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>,
239 fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>,
244 fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>,
249 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
253 pinctrl_usb1_connector: usb1-connectorgrp {
254 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
258 fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>;
262 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
271 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
272 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
281 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
282 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,