dts/freescale/imx8-ss-dma.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 	compatible = "simple-bus";
12 	#address-cells = <1>;
13 	#size-cells = <1>;
16 	dma_ipg_clk: clock-dma-ipg {
17 		compatible = "fixed-clock";
18 		#clock-cells = <0>;
19 		clock-frequency = <120000000>;
20 		clock-output-names = "dma_ipg_clk";
24 		compatible = "fsl,imx7ulp-spi";
26 		#address-cells = <1>;
27 		#size-cells = <0>;
29 		interrupt-parent = <&gic>;
32 		clock-names = "per", "ipg";
33 		assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
34 		assigned-clock-rates = <60000000>;
35 		power-domains = <&pd IMX_SC_R_SPI_0>;
40 		compatible = "fsl,imx7ulp-spi";
42 		#address-cells = <1>;
43 		#size-cells = <0>;
45 		interrupt-parent = <&gic>;
48 		clock-names = "per", "ipg";
49 		assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
50 		assigned-clock-rates = <60000000>;
51 		power-domains = <&pd IMX_SC_R_SPI_1>;
56 		compatible = "fsl,imx7ulp-spi";
58 		#address-cells = <1>;
59 		#size-cells = <0>;
61 		interrupt-parent = <&gic>;
64 		clock-names = "per", "ipg";
65 		assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
66 		assigned-clock-rates = <60000000>;
67 		power-domains = <&pd IMX_SC_R_SPI_2>;
72 		compatible = "fsl,imx7ulp-spi";
74 		#address-cells = <1>;
75 		#size-cells = <0>;
77 		interrupt-parent = <&gic>;
80 		clock-names = "per", "ipg";
81 		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
82 		assigned-clock-rates = <60000000>;
83 		power-domains = <&pd IMX_SC_R_SPI_3>;
92 		clock-names = "ipg", "baud";
93 		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
94 		assigned-clock-rates = <80000000>;
95 		power-domains = <&pd IMX_SC_R_UART_0>;
104 		clock-names = "ipg", "baud";
105 		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
106 		assigned-clock-rates = <80000000>;
107 		power-domains = <&pd IMX_SC_R_UART_1>;
116 		clock-names = "ipg", "baud";
117 		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
118 		assigned-clock-rates = <80000000>;
119 		power-domains = <&pd IMX_SC_R_UART_2>;
128 		clock-names = "ipg", "baud";
129 		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
130 		assigned-clock-rates = <80000000>;
131 		power-domains = <&pd IMX_SC_R_UART_3>;
135 	spi0_lpcg: clock-controller@5a400000 {
136 		compatible = "fsl,imx8qxp-lpcg";
138 		#clock-cells = <1>;
141 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
142 		clock-output-names = "spi0_lpcg_clk",
144 		power-domains = <&pd IMX_SC_R_SPI_0>;
147 	spi1_lpcg: clock-controller@5a410000 {
148 		compatible = "fsl,imx8qxp-lpcg";
150 		#clock-cells = <1>;
153 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
154 		clock-output-names = "spi1_lpcg_clk",
156 		power-domains = <&pd IMX_SC_R_SPI_1>;
159 	spi2_lpcg: clock-controller@5a420000 {
160 		compatible = "fsl,imx8qxp-lpcg";
162 		#clock-cells = <1>;
165 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
166 		clock-output-names = "spi2_lpcg_clk",
168 		power-domains = <&pd IMX_SC_R_SPI_2>;
171 	spi3_lpcg: clock-controller@5a430000 {
172 		compatible = "fsl,imx8qxp-lpcg";
174 		#clock-cells = <1>;
177 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
178 		clock-output-names = "spi3_lpcg_clk",
180 		power-domains = <&pd IMX_SC_R_SPI_3>;
183 	uart0_lpcg: clock-controller@5a460000 {
184 		compatible = "fsl,imx8qxp-lpcg";
186 		#clock-cells = <1>;
189 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
190 		clock-output-names = "uart0_lpcg_baud_clk",
192 		power-domains = <&pd IMX_SC_R_UART_0>;
195 	uart1_lpcg: clock-controller@5a470000 {
196 		compatible = "fsl,imx8qxp-lpcg";
198 		#clock-cells = <1>;
201 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
202 		clock-output-names = "uart1_lpcg_baud_clk",
204 		power-domains = <&pd IMX_SC_R_UART_1>;
207 	uart2_lpcg: clock-controller@5a480000 {
208 		compatible = "fsl,imx8qxp-lpcg";
210 		#clock-cells = <1>;
213 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
214 		clock-output-names = "uart2_lpcg_baud_clk",
216 		power-domains = <&pd IMX_SC_R_UART_2>;
219 	uart3_lpcg: clock-controller@5a490000 {
220 		compatible = "fsl,imx8qxp-lpcg";
222 		#clock-cells = <1>;
225 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
226 		clock-output-names = "uart3_lpcg_baud_clk",
228 		power-domains = <&pd IMX_SC_R_UART_3>;
236 		clock-names = "per", "ipg";
237 		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
238 		assigned-clock-rates = <24000000>;
239 		power-domains = <&pd IMX_SC_R_I2C_0>;
248 		clock-names = "per", "ipg";
249 		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
250 		assigned-clock-rates = <24000000>;
251 		power-domains = <&pd IMX_SC_R_I2C_1>;
260 		clock-names = "per", "ipg";
261 		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
262 		assigned-clock-rates = <24000000>;
263 		power-domains = <&pd IMX_SC_R_I2C_2>;
272 		clock-names = "per", "ipg";
273 		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
274 		assigned-clock-rates = <24000000>;
275 		power-domains = <&pd IMX_SC_R_I2C_3>;
280 		compatible = "nxp,imx8qxp-adc";
281 		#io-channel-cells = <1>;
284 		interrupt-parent = <&gic>;
287 		clock-names = "per", "ipg";
288 		assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
289 		assigned-clock-rates = <24000000>;
290 		power-domains = <&pd IMX_SC_R_ADC_0>;
295 		compatible = "nxp,imx8qxp-adc";
296 		#io-channel-cells = <1>;
299 		interrupt-parent = <&gic>;
302 		clock-names = "per", "ipg";
303 		assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
304 		assigned-clock-rates = <24000000>;
305 		power-domains = <&pd IMX_SC_R_ADC_1>;
310 		compatible = "fsl,imx8qm-flexcan";
313 		interrupt-parent = <&gic>;
316 		clock-names = "ipg", "per";
317 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
318 		assigned-clock-rates = <40000000>;
319 		power-domains = <&pd IMX_SC_R_CAN_0>;
321 		fsl,clk-source = /bits/ 8 <0>;
322 		fsl,scu-index = /bits/ 8 <0>;
327 		compatible = "fsl,imx8qm-flexcan";
330 		interrupt-parent = <&gic>;
337 		clock-names = "ipg", "per";
338 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
339 		assigned-clock-rates = <40000000>;
340 		power-domains = <&pd IMX_SC_R_CAN_1>;
342 		fsl,clk-source = /bits/ 8 <0>;
343 		fsl,scu-index = /bits/ 8 <1>;
348 		compatible = "fsl,imx8qm-flexcan";
351 		interrupt-parent = <&gic>;
358 		clock-names = "ipg", "per";
359 		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
360 		assigned-clock-rates = <40000000>;
361 		power-domains = <&pd IMX_SC_R_CAN_2>;
363 		fsl,clk-source = /bits/ 8 <0>;
364 		fsl,scu-index = /bits/ 8 <2>;
368 	i2c0_lpcg: clock-controller@5ac00000 {
369 		compatible = "fsl,imx8qxp-lpcg";
371 		#clock-cells = <1>;
374 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
375 		clock-output-names = "i2c0_lpcg_clk",
377 		power-domains = <&pd IMX_SC_R_I2C_0>;
380 	i2c1_lpcg: clock-controller@5ac10000 {
381 		compatible = "fsl,imx8qxp-lpcg";
383 		#clock-cells = <1>;
386 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
387 		clock-output-names = "i2c1_lpcg_clk",
389 		power-domains = <&pd IMX_SC_R_I2C_1>;
392 	i2c2_lpcg: clock-controller@5ac20000 {
393 		compatible = "fsl,imx8qxp-lpcg";
395 		#clock-cells = <1>;
398 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
399 		clock-output-names = "i2c2_lpcg_clk",
401 		power-domains = <&pd IMX_SC_R_I2C_2>;
404 	i2c3_lpcg: clock-controller@5ac30000 {
405 		compatible = "fsl,imx8qxp-lpcg";
407 		#clock-cells = <1>;
410 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
411 		clock-output-names = "i2c3_lpcg_clk",
413 		power-domains = <&pd IMX_SC_R_I2C_3>;
416 	adc0_lpcg: clock-controller@5ac80000 {
417 		compatible = "fsl,imx8qxp-lpcg";
419 		#clock-cells = <1>;
422 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
423 		clock-output-names = "adc0_lpcg_clk",
425 		power-domains = <&pd IMX_SC_R_ADC_0>;
428 	adc1_lpcg: clock-controller@5ac90000 {
429 		compatible = "fsl,imx8qxp-lpcg";
431 		#clock-cells = <1>;
434 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
435 		clock-output-names = "adc1_lpcg_clk",
437 		power-domains = <&pd IMX_SC_R_ADC_1>;
440 	can0_lpcg: clock-controller@5acd0000 {
441 		compatible = "fsl,imx8qxp-lpcg";
443 		#clock-cells = <1>;
446 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
447 		clock-output-names = "can0_lpcg_pe_clk",
450 		power-domains = <&pd IMX_SC_R_CAN_0>;