Lines Matching +full:crit +full:- +full:soc +full:- +full:level
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
303 cache-unified;
304 cache-size = <0x100000>;
305 cache-line-size = <64>;
306 cache-sets = <1024>;
307 cache-level = <2>;
310 cluster1_l2: l2-cache1 {
312 cache-unified;
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
319 cluster2_l2: l2-cache2 {
321 cache-unified;
322 cache-size = <0x100000>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
328 cluster3_l2: l2-cache3 {
330 cache-unified;
331 cache-size = <0x100000>;
332 cache-line-size = <64>;
333 cache-sets = <1024>;
334 cache-level = <2>;
337 cluster4_l2: l2-cache4 {
339 cache-unified;
340 cache-size = <0x100000>;
341 cache-line-size = <64>;
342 cache-sets = <1024>;
343 cache-level = <2>;
346 cluster5_l2: l2-cache5 {
348 cache-unified;
349 cache-size = <0x100000>;
350 cache-line-size = <64>;
351 cache-sets = <1024>;
352 cache-level = <2>;
355 cluster6_l2: l2-cache6 {
357 cache-unified;
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
360 cache-sets = <1024>;
361 cache-level = <2>;
364 cluster7_l2: l2-cache7 {
366 cache-unified;
367 cache-size = <0x100000>;
368 cache-line-size = <64>;
369 cache-sets = <1024>;
370 cache-level = <2>;
373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle-state";
375 idle-state-name = "PW15";
376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <2000>;
378 exit-latency-us = <2000>;
379 min-residency-us = <6000>;
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
393 #size-cells = <2>;
395 interrupt-controller;
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-v3-its";
400 msi-controller;
406 compatible = "arm,armv8-timer";
414 compatible = "arm,cortex-a72-pmu";
419 compatible = "arm,psci-0.2";
424 // DRAM space - 1, size : 2 GB DRAM
429 ddr1: memory-controller@1080000 {
430 compatible = "fsl,qoriq-memory-controller";
433 little-endian;
436 ddr2: memory-controller@1090000 {
437 compatible = "fsl,qoriq-memory-controller";
440 little-endian;
443 // One clock unit-sysclk node which bootloader require during DT fix-up
445 compatible = "fixed-clock";
446 #clock-cells = <0>;
447 clock-frequency = <100000000>; // fixed up by bootloader
448 clock-output-names = "sysclk";
451 thermal-zones {
452 cluster6-7 {
453 polling-delay-passive = <1000>;
454 polling-delay = <5000>;
455 thermal-sensors = <&tmu 0>;
458 cluster6_7_alert: cluster6-7-alert {
464 cluster6_7_crit: cluster6-7-crit {
471 cooling-maps {
474 cooling-device =
495 ddr-cluster5 {
496 polling-delay-passive = <1000>;
497 polling-delay = <5000>;
498 thermal-sensors = <&tmu 1>;
501 ddr-cluster5-alert {
507 ddr-cluster5-crit {
516 polling-delay-passive = <1000>;
517 polling-delay = <5000>;
518 thermal-sensors = <&tmu 2>;
521 wriop-alert {
527 wriop-crit {
535 dce-qbman-hsio2 {
536 polling-delay-passive = <1000>;
537 polling-delay = <5000>;
538 thermal-sensors = <&tmu 3>;
541 dce-qbman-alert {
547 dce-qbman-crit {
555 ccn-dpaa-tbu {
556 polling-delay-passive = <1000>;
557 polling-delay = <5000>;
558 thermal-sensors = <&tmu 4>;
561 ccn-dpaa-alert {
567 ccn-dpaa-crit {
575 cluster4-hsio3 {
576 polling-delay-passive = <1000>;
577 polling-delay = <5000>;
578 thermal-sensors = <&tmu 5>;
581 clust4-hsio3-alert {
587 clust4-hsio3-crit {
595 cluster2-3 {
596 polling-delay-passive = <1000>;
597 polling-delay = <5000>;
598 thermal-sensors = <&tmu 6>;
601 cluster2-3-alert {
607 cluster2-3-crit {
616 soc {
617 compatible = "simple-bus";
618 #address-cells = <2>;
619 #size-cells = <2>;
621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
624 compatible = "fsl,lynx-28g";
626 #phy-cells = <1>;
630 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
631 fsl,sec-era = <10>;
632 #address-cells = <1>;
633 #size-cells = <1>;
637 dma-coherent;
641 compatible = "fsl,sec-v5.0-job-ring",
642 "fsl,sec-v4.0-job-ring";
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
655 compatible = "fsl,sec-v5.0-job-ring",
656 "fsl,sec-v4.0-job-ring";
662 compatible = "fsl,sec-v5.0-job-ring",
663 "fsl,sec-v4.0-job-ring";
669 clockgen: clock-controller@1300000 {
670 compatible = "fsl,lx2160a-clockgen";
672 #clock-cells = <2>;
677 compatible = "fsl,lx2160a-dcfg", "syscon";
679 little-endian;
683 compatible = "fsl,ls1028a-sfp";
687 clock-names = "sfp";
691 compatible = "fsl,lx2160a-isc", "syscon";
693 little-endian;
694 #address-cells = <1>;
695 #size-cells = <1>;
698 extirq: interrupt-controller@14 {
699 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
700 #interrupt-cells = <2>;
701 #address-cells = <0>;
702 interrupt-controller;
704 interrupt-map =
717 interrupt-map-mask = <0xf 0x0>;
722 compatible = "fsl,qoriq-tmu";
725 fsl,tmu-range = <0x800000e6 0x8001017d>;
726 fsl,tmu-calibration =
731 little-endian;
732 #thermal-sensor-cells = <1>;
736 compatible = "fsl,vf610-i2c";
737 #address-cells = <1>;
738 #size-cells = <0>;
741 clock-names = "i2c";
744 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
749 compatible = "fsl,vf610-i2c";
750 #address-cells = <1>;
751 #size-cells = <0>;
754 clock-names = "i2c";
761 compatible = "fsl,vf610-i2c";
762 #address-cells = <1>;
763 #size-cells = <0>;
766 clock-names = "i2c";
773 compatible = "fsl,vf610-i2c";
774 #address-cells = <1>;
775 #size-cells = <0>;
778 clock-names = "i2c";
785 compatible = "fsl,vf610-i2c";
786 #address-cells = <1>;
787 #size-cells = <0>;
790 clock-names = "i2c";
793 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
798 compatible = "fsl,vf610-i2c";
799 #address-cells = <1>;
800 #size-cells = <0>;
803 clock-names = "i2c";
810 compatible = "fsl,vf610-i2c";
811 #address-cells = <1>;
812 #size-cells = <0>;
815 clock-names = "i2c";
822 compatible = "fsl,vf610-i2c";
823 #address-cells = <1>;
824 #size-cells = <0>;
827 clock-names = "i2c";
834 compatible = "nxp,lx2160a-fspi";
835 #address-cells = <1>;
836 #size-cells = <0>;
839 reg-names = "fspi_base", "fspi_mmap";
845 clock-names = "fspi_en", "fspi";
850 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
851 #address-cells = <1>;
852 #size-cells = <0>;
857 clock-names = "dspi";
858 spi-num-chipselects = <5>;
859 bus-num = <0>;
864 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
865 #address-cells = <1>;
866 #size-cells = <0>;
871 clock-names = "dspi";
872 spi-num-chipselects = <5>;
873 bus-num = <1>;
878 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
879 #address-cells = <1>;
880 #size-cells = <0>;
885 clock-names = "dspi";
886 spi-num-chipselects = <5>;
887 bus-num = <2>;
894 interrupts = <0 28 0x4>; /* Level high type */
897 dma-coherent;
898 voltage-ranges = <1800 1800 3300 3300>;
899 sdhci,auto-cmd12;
900 little-endian;
901 bus-width = <4>;
908 interrupts = <0 63 0x4>; /* Level high type */
911 dma-coherent;
912 voltage-ranges = <1800 1800 3300 3300>;
913 sdhci,auto-cmd12;
914 broken-cd;
915 little-endian;
916 bus-width = <4>;
921 compatible = "fsl,lx2160ar1-flexcan";
927 clock-names = "ipg", "per";
928 fsl,clk-source = /bits/ 8 <0>;
933 compatible = "fsl,lx2160ar1-flexcan";
939 clock-names = "ipg", "per";
940 fsl,clk-source = /bits/ 8 <0>;
945 compatible = "arm,sbsa-uart","arm,pl011";
948 current-speed = <115200>;
953 compatible = "arm,sbsa-uart","arm,pl011";
956 current-speed = <115200>;
961 compatible = "arm,sbsa-uart","arm,pl011";
964 current-speed = <115200>;
969 compatible = "arm,sbsa-uart","arm,pl011";
972 current-speed = <115200>;
977 compatible = "fsl,qoriq-gpio";
980 gpio-controller;
981 little-endian;
982 #gpio-cells = <2>;
983 interrupt-controller;
984 #interrupt-cells = <2>;
988 compatible = "fsl,qoriq-gpio";
991 gpio-controller;
992 little-endian;
993 #gpio-cells = <2>;
994 interrupt-controller;
995 #interrupt-cells = <2>;
999 compatible = "fsl,qoriq-gpio";
1002 gpio-controller;
1003 little-endian;
1004 #gpio-cells = <2>;
1005 interrupt-controller;
1006 #interrupt-cells = <2>;
1010 compatible = "fsl,qoriq-gpio";
1013 gpio-controller;
1014 little-endian;
1015 #gpio-cells = <2>;
1016 interrupt-controller;
1017 #interrupt-cells = <2>;
1021 compatible = "arm,sbsa-gwdt";
1025 timeout-sec = <30>;
1028 rcpm: power-controller@1e34040 {
1029 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1031 #fsl,rcpm-wakeup-cells = <7>;
1032 little-endian;
1036 compatible = "fsl,lx2160a-ftm-alarm";
1038 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1047 snps,quirk-frame-length-adjustment = <0x20>;
1048 usb3-lpm-capable;
1050 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1059 snps,quirk-frame-length-adjustment = <0x20>;
1060 usb3-lpm-capable;
1062 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1067 compatible = "fsl,lx2160a-ahci";
1070 reg-names = "ahci", "sata-ecc";
1074 dma-coherent;
1079 compatible = "fsl,lx2160a-ahci";
1082 reg-names = "ahci", "sata-ecc";
1086 dma-coherent;
1091 compatible = "fsl,lx2160a-ahci";
1094 reg-names = "ahci", "sata-ecc";
1098 dma-coherent;
1103 compatible = "fsl,lx2160a-ahci";
1106 reg-names = "ahci", "sata-ecc";
1110 dma-coherent;
1115 compatible = "fsl,lx2160a-pcie";
1118 reg-names = "csr_axi_slave", "config_axi_slave";
1122 interrupt-names = "aer", "pme", "intr";
1123 #address-cells = <3>;
1124 #size-cells = <2>;
1126 dma-coherent;
1127 apio-wins = <8>;
1128 ppio-wins = <8>;
1129 bus-range = <0x0 0xff>;
1130 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1131 msi-parent = <&its>;
1132 #interrupt-cells = <1>;
1133 interrupt-map-mask = <0 0 0 7>;
1134 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1138 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1143 compatible = "fsl,lx2160a-pcie";
1146 reg-names = "csr_axi_slave", "config_axi_slave";
1150 interrupt-names = "aer", "pme", "intr";
1151 #address-cells = <3>;
1152 #size-cells = <2>;
1154 dma-coherent;
1155 apio-wins = <8>;
1156 ppio-wins = <8>;
1157 bus-range = <0x0 0xff>;
1158 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1159 msi-parent = <&its>;
1160 #interrupt-cells = <1>;
1161 interrupt-map-mask = <0 0 0 7>;
1162 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1166 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1171 compatible = "fsl,lx2160a-pcie";
1174 reg-names = "csr_axi_slave", "config_axi_slave";
1178 interrupt-names = "aer", "pme", "intr";
1179 #address-cells = <3>;
1180 #size-cells = <2>;
1182 dma-coherent;
1183 apio-wins = <256>;
1184 ppio-wins = <24>;
1185 bus-range = <0x0 0xff>;
1186 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1187 msi-parent = <&its>;
1188 #interrupt-cells = <1>;
1189 interrupt-map-mask = <0 0 0 7>;
1190 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1194 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1199 compatible = "fsl,lx2160a-pcie";
1202 reg-names = "csr_axi_slave", "config_axi_slave";
1206 interrupt-names = "aer", "pme", "intr";
1207 #address-cells = <3>;
1208 #size-cells = <2>;
1210 dma-coherent;
1211 apio-wins = <8>;
1212 ppio-wins = <8>;
1213 bus-range = <0x0 0xff>;
1214 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1215 msi-parent = <&its>;
1216 #interrupt-cells = <1>;
1217 interrupt-map-mask = <0 0 0 7>;
1218 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1222 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1227 compatible = "fsl,lx2160a-pcie";
1230 reg-names = "csr_axi_slave", "config_axi_slave";
1234 interrupt-names = "aer", "pme", "intr";
1235 #address-cells = <3>;
1236 #size-cells = <2>;
1238 dma-coherent;
1239 apio-wins = <256>;
1240 ppio-wins = <24>;
1241 bus-range = <0x0 0xff>;
1242 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1243 msi-parent = <&its>;
1244 #interrupt-cells = <1>;
1245 interrupt-map-mask = <0 0 0 7>;
1246 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1250 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1255 compatible = "fsl,lx2160a-pcie";
1258 reg-names = "csr_axi_slave", "config_axi_slave";
1262 interrupt-names = "aer", "pme", "intr";
1263 #address-cells = <3>;
1264 #size-cells = <2>;
1266 dma-coherent;
1267 apio-wins = <8>;
1268 ppio-wins = <8>;
1269 bus-range = <0x0 0xff>;
1270 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1271 msi-parent = <&its>;
1272 #interrupt-cells = <1>;
1273 interrupt-map-mask = <0 0 0 7>;
1274 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1278 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1283 compatible = "arm,mmu-500";
1285 #iommu-cells = <1>;
1286 #global-interrupts = <14>;
1291 // global non-secure fault
1293 // combined non-secure
1295 // performance counter interrupts 0-9
1371 dma-coherent;
1375 compatible = "fsl,dpaa2-console";
1379 ptp-timer@8b95000 {
1380 compatible = "fsl,dpaa2-ptp";
1384 little-endian;
1385 fsl,extts-fifo;
1388 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1390 compatible = "fsl,fman-memac-mdio";
1393 #address-cells = <1>;
1394 #size-cells = <0>;
1395 little-endian;
1396 clock-frequency = <2500000>;
1403 compatible = "fsl,fman-memac-mdio";
1406 little-endian;
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1409 clock-frequency = <2500000>;
1416 compatible = "fsl,fman-memac-mdio";
1418 little-endian;
1419 #address-cells = <1>;
1420 #size-cells = <0>;
1423 pcs1: ethernet-phy@0 {
1429 compatible = "fsl,fman-memac-mdio";
1431 little-endian;
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1436 pcs2: ethernet-phy@0 {
1442 compatible = "fsl,fman-memac-mdio";
1444 little-endian;
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1449 pcs3: ethernet-phy@0 {
1455 compatible = "fsl,fman-memac-mdio";
1457 little-endian;
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1462 pcs4: ethernet-phy@0 {
1468 compatible = "fsl,fman-memac-mdio";
1470 little-endian;
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1475 pcs5: ethernet-phy@0 {
1481 compatible = "fsl,fman-memac-mdio";
1483 little-endian;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1488 pcs6: ethernet-phy@0 {
1494 compatible = "fsl,fman-memac-mdio";
1496 little-endian;
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1501 pcs7: ethernet-phy@0 {
1507 compatible = "fsl,fman-memac-mdio";
1509 little-endian;
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1514 pcs8: ethernet-phy@0 {
1520 compatible = "fsl,fman-memac-mdio";
1522 little-endian;
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1527 pcs9: ethernet-phy@0 {
1533 compatible = "fsl,fman-memac-mdio";
1535 little-endian;
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1540 pcs10: ethernet-phy@0 {
1546 compatible = "fsl,fman-memac-mdio";
1548 little-endian;
1549 #address-cells = <1>;
1550 #size-cells = <0>;
1553 pcs11: ethernet-phy@0 {
1559 compatible = "fsl,fman-memac-mdio";
1561 little-endian;
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1566 pcs12: ethernet-phy@0 {
1572 compatible = "fsl,fman-memac-mdio";
1574 little-endian;
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1579 pcs13: ethernet-phy@0 {
1585 compatible = "fsl,fman-memac-mdio";
1587 little-endian;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1592 pcs14: ethernet-phy@0 {
1598 compatible = "fsl,fman-memac-mdio";
1600 little-endian;
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1605 pcs15: ethernet-phy@0 {
1611 compatible = "fsl,fman-memac-mdio";
1613 little-endian;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1618 pcs16: ethernet-phy@0 {
1624 compatible = "fsl,fman-memac-mdio";
1626 little-endian;
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1631 pcs17: ethernet-phy@0 {
1637 compatible = "fsl,fman-memac-mdio";
1639 little-endian;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1644 pcs18: ethernet-phy@0 {
1649 fsl_mc: fsl-mc@80c000000 {
1650 compatible = "fsl,qoriq-mc";
1653 msi-parent = <&its>;
1654 /* iommu-map property is fixed up by u-boot */
1655 iommu-map = <0 &smmu 0 0>;
1656 dma-coherent;
1657 #address-cells = <3>;
1658 #size-cells = <1>;
1661 * Region type 0x0 - MC portals
1662 * Region type 0x1 - QBMAN portals
1668 * Define the maximum number of MACs present on the SoC.
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1675 compatible = "fsl,qoriq-mc-dpmac";
1677 pcs-handle = <&pcs1>;
1681 compatible = "fsl,qoriq-mc-dpmac";
1683 pcs-handle = <&pcs2>;
1687 compatible = "fsl,qoriq-mc-dpmac";
1689 pcs-handle = <&pcs3>;
1693 compatible = "fsl,qoriq-mc-dpmac";
1695 pcs-handle = <&pcs4>;
1699 compatible = "fsl,qoriq-mc-dpmac";
1701 pcs-handle = <&pcs5>;
1705 compatible = "fsl,qoriq-mc-dpmac";
1707 pcs-handle = <&pcs6>;
1711 compatible = "fsl,qoriq-mc-dpmac";
1713 pcs-handle = <&pcs7>;
1717 compatible = "fsl,qoriq-mc-dpmac";
1719 pcs-handle = <&pcs8>;
1723 compatible = "fsl,qoriq-mc-dpmac";
1725 pcs-handle = <&pcs9>;
1729 compatible = "fsl,qoriq-mc-dpmac";
1731 pcs-handle = <&pcs10>;
1735 compatible = "fsl,qoriq-mc-dpmac";
1737 pcs-handle = <&pcs11>;
1741 compatible = "fsl,qoriq-mc-dpmac";
1743 pcs-handle = <&pcs12>;
1747 compatible = "fsl,qoriq-mc-dpmac";
1749 pcs-handle = <&pcs13>;
1753 compatible = "fsl,qoriq-mc-dpmac";
1755 pcs-handle = <&pcs14>;
1759 compatible = "fsl,qoriq-mc-dpmac";
1761 pcs-handle = <&pcs15>;
1765 compatible = "fsl,qoriq-mc-dpmac";
1767 pcs-handle = <&pcs16>;
1771 compatible = "fsl,qoriq-mc-dpmac";
1773 pcs-handle = <&pcs17>;
1777 compatible = "fsl,qoriq-mc-dpmac";
1779 pcs-handle = <&pcs18>;
1787 compatible = "linaro,optee-tz";