Lines Matching +full:0 +full:x1ee0000
37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
102 arm,psci-suspend-param = <0x0>;
111 reg = <0x0 0x80000000 0 0x80000000>;
122 size = <0 0x1000000>;
123 alignment = <0 0x1000000>;
129 size = <0 0x400000>;
130 alignment = <0 0x400000>;
136 size = <0 0x2000000>;
137 alignment = <0 0x2000000>;
144 #clock-cells = <0>;
152 offset = <0xb0>;
153 mask = <0x02>;
160 thermal-sensors = <&tmu 0>;
271 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <1 11 0xf08>, /* Virtual PPI */
274 <1 10 0xf08>; /* Hypervisor PPI */
280 interrupts = <0 106 0x4>,
281 <0 107 0x4>,
282 <0 95 0x4>,
283 <0 97 0x4>;
294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <1 9 0xf08>;
306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
311 reg = <0x0 0x1ee1000 0x0 0x1000>;
318 reg = <0x0 0x1570000 0x0 0x10000>;
322 ranges = <0x0 0x0 0x1570000 0x10000>;
327 #address-cells = <0>;
329 reg = <0x1ac 4>;
331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map-mask = <0xf 0x0>;
348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec-v4.0";
353 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <0 75 0x4>;
360 "fsl,sec-v5.0-job-ring",
361 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 0x10000>;
363 interrupts = <0 71 0x4>;
368 "fsl,sec-v5.0-job-ring",
369 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 0x10000>;
371 interrupts = <0 72 0x4>;
376 "fsl,sec-v5.0-job-ring",
377 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 0x10000>;
379 interrupts = <0 73 0x4>;
384 "fsl,sec-v5.0-job-ring",
385 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 0x10000>;
387 interrupts = <0 74 0x4>;
393 reg = <0x0 0x1e80000 0x0 0x10000>;
401 reg = <0x0 0x1ee0000 0x0 0x1000>;
407 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <0 43 0x4>;
414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x40000000 0x0 0x4000000>;
418 interrupts = <0 99 0x4>;
429 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <0 62 0x4>;
431 clock-frequency = <0>;
440 reg = <0x0 0x1080000 0x0 0x1000>;
441 interrupts = <0 144 0x4>;
447 reg = <0x0 0x1f00000 0x0 0x10000>;
448 interrupts = <0 33 0x4>;
449 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
450 fsl,tmu-calibration = <0x00000000 0x00000023
451 0x00000001 0x0000002a
452 0x00000002 0x00000031
453 0x00000003 0x00000037
454 0x00000004 0x0000003e
455 0x00000005 0x00000044
456 0x00000006 0x0000004b
457 0x00000007 0x00000051
458 0x00000008 0x00000058
459 0x00000009 0x0000005e
460 0x0000000a 0x00000065
461 0x0000000b 0x0000006b
463 0x00010000 0x00000023
464 0x00010001 0x0000002b
465 0x00010002 0x00000033
466 0x00010003 0x0000003b
467 0x00010004 0x00000043
468 0x00010005 0x0000004b
469 0x00010006 0x00000054
470 0x00010007 0x0000005c
471 0x00010008 0x00000064
472 0x00010009 0x0000006c
474 0x00020000 0x00000021
475 0x00020001 0x0000002c
476 0x00020002 0x00000036
477 0x00020003 0x00000040
478 0x00020004 0x0000004b
479 0x00020005 0x00000055
480 0x00020006 0x0000005f
482 0x00030000 0x00000013
483 0x00030001 0x0000001d
484 0x00030002 0x00000028
485 0x00030003 0x00000032
486 0x00030004 0x0000003d
487 0x00030005 0x00000047
488 0x00030006 0x00000052
489 0x00030007 0x0000005c>;
495 reg = <0x0 0x1880000 0x0 0x10000>;
502 reg = <0x0 0x1890000 0x0 0x10000>;
508 ranges = <0x0 0x5 0x08000000 0x8000000>;
512 ranges = <0x0 0x5 0x00000000 0x8000000>;
516 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
518 #size-cells = <0>;
519 reg = <0x0 0x2100000 0x0 0x10000>;
520 interrupts = <0 64 0x4>;
530 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
532 #size-cells = <0>;
533 reg = <0x0 0x2110000 0x0 0x10000>;
534 interrupts = <0 65 0x4>;
546 #size-cells = <0>;
547 reg = <0x0 0x2180000 0x0 0x10000>;
548 interrupts = <0 56 0x4>;
561 #size-cells = <0>;
562 reg = <0x0 0x2190000 0x0 0x10000>;
563 interrupts = <0 57 0x4>;
574 #size-cells = <0>;
575 reg = <0x0 0x21a0000 0x0 0x10000>;
576 interrupts = <0 58 0x4>;
587 #size-cells = <0>;
588 reg = <0x0 0x21b0000 0x0 0x10000>;
589 interrupts = <0 59 0x4>;
599 reg = <0x00 0x21c0500 0x0 0x100>;
600 interrupts = <0 54 0x4>;
607 reg = <0x00 0x21c0600 0x0 0x100>;
608 interrupts = <0 54 0x4>;
615 reg = <0x0 0x21d0500 0x0 0x100>;
616 interrupts = <0 55 0x4>;
623 reg = <0x0 0x21d0600 0x0 0x100>;
624 interrupts = <0 55 0x4>;
631 reg = <0x0 0x2300000 0x0 0x10000>;
632 interrupts = <0 66 0x4>;
641 reg = <0x0 0x2310000 0x0 0x10000>;
642 interrupts = <0 67 0x4>;
651 reg = <0x0 0x2320000 0x0 0x10000>;
652 interrupts = <0 68 0x4>;
661 reg = <0x0 0x2330000 0x0 0x10000>;
662 interrupts = <0 134 0x4>;
673 ranges = <0x0 0x0 0x2400000 0x40000>;
674 reg = <0x0 0x2400000 0x0 0x480>;
682 reg = <0x80 0x80>;
683 #address-cells = <0>;
692 #size-cells = <0>;
695 reg = <0x700 0x80>;
703 reg = <0x1000 0x800>;
708 reg = <0x2000 0x200>;
715 reg = <0x2200 0x200>;
724 ranges = <0x0 0x10000 0x6000>;
726 data-only@0 {
729 reg = <0x0 0x6000>;
736 reg = <0x0 0x2950000 0x0 0x1000>;
737 interrupts = <0 48 0x4>;
738 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
745 reg = <0x0 0x2960000 0x0 0x1000>;
746 interrupts = <0 49 0x4>;
755 reg = <0x0 0x2970000 0x0 0x1000>;
756 interrupts = <0 50 0x4>;
765 reg = <0x0 0x2980000 0x0 0x1000>;
766 interrupts = <0 51 0x4>;
775 reg = <0x0 0x2990000 0x0 0x1000>;
776 interrupts = <0 52 0x4>;
785 reg = <0x0 0x29a0000 0x0 0x1000>;
786 interrupts = <0 53 0x4>;
795 reg = <0x0 0x2ad0000 0x0 0x10000>;
796 interrupts = <0 83 0x4>;
806 reg = <0x0 0x2c00000 0x0 0x10000>,
807 <0x0 0x2c10000 0x0 0x10000>,
808 <0x0 0x2c20000 0x0 0x10000>;
809 interrupts = <0 103 0x4>,
810 <0 103 0x4>;
826 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
830 reg = <0x0 0x2f00000 0x0 0x10000>;
831 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
833 snps,quirk-frame-length-adjustment = <0x20>;
842 reg = <0x0 0x3000000 0x0 0x10000>;
843 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
845 snps,quirk-frame-length-adjustment = <0x20>;
854 reg = <0x0 0x3100000 0x0 0x10000>;
855 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
857 snps,quirk-frame-length-adjustment = <0x20>;
866 reg = <0x0 0x3200000 0x0 0x10000>,
867 <0x0 0x20140520 0x0 0x4>;
869 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
878 reg = <0x0 0x1571000 0x0 0x8>;
880 interrupts = <0 116 0x4>;
885 reg = <0x0 0x1572000 0x0 0x8>;
887 interrupts = <0 126 0x4>;
892 reg = <0x0 0x1573000 0x0 0x8>;
894 interrupts = <0 160 0x4>;
899 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
900 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
902 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
903 <0 118 IRQ_TYPE_LEVEL_HIGH>;
909 bus-range = <0x0 0xff>;
910 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
911 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
914 interrupt-map-mask = <0 0 0 7>;
915 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
916 <0000 0 0 2 &gic 0 111 0x4>,
917 <0000 0 0 3 &gic 0 112 0x4>,
918 <0000 0 0 4 &gic 0 113 0x4>;
919 fsl,pcie-scfg = <&scfg 0>;
926 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
927 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
929 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
930 <0 128 IRQ_TYPE_LEVEL_HIGH>;
936 bus-range = <0x0 0xff>;
937 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
938 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
941 interrupt-map-mask = <0 0 0 7>;
942 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
943 <0000 0 0 2 &gic 0 121 0x4>,
944 <0000 0 0 3 &gic 0 122 0x4>,
945 <0000 0 0 4 &gic 0 123 0x4>;
953 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
954 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
956 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
957 <0 162 IRQ_TYPE_LEVEL_HIGH>;
963 bus-range = <0x0 0xff>;
964 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
965 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
968 interrupt-map-mask = <0 0 0 7>;
969 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
970 <0000 0 0 2 &gic 0 155 0x4>,
971 <0000 0 0 3 &gic 0 156 0x4>,
972 <0000 0 0 4 &gic 0 157 0x4>;
980 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
981 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
982 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
992 block-offset = <0x10000>;
1001 reg = <0x0 0x1ee2140 0x0 0x4>;
1007 reg = <0x0 0x29d0000 0x0 0x10000>;
1008 fsl,rcpm-wakeup = <&rcpm 0x20000>;