Lines Matching full:cmu_top
368 cmu_top: clock-controller@10030000 { label
432 <&cmu_top CLK_ACLK_FSYS_200>,
433 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
434 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
435 <&cmu_top CLK_SCLK_MMC2_FSYS>,
436 <&cmu_top CLK_SCLK_MMC1_FSYS>,
437 <&cmu_top CLK_SCLK_MMC0_FSYS>,
438 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
439 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
451 <&cmu_top CLK_ACLK_G2D_266>,
452 <&cmu_top CLK_ACLK_G2D_400>;
487 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
497 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
506 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
524 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
537 <&cmu_top CLK_ACLK_GSCL_111>,
538 <&cmu_top CLK_ACLK_GSCL_333>;
569 <&cmu_top CLK_SCLK_JPEG_MSCL>,
570 <&cmu_top CLK_ACLK_MSCL_400>;
580 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
590 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
603 <&cmu_top CLK_ACLK_ISP_DIS_400>,
604 <&cmu_top CLK_ACLK_ISP_400>;
618 <&cmu_top CLK_ACLK_CAM0_333>,
619 <&cmu_top CLK_ACLK_CAM0_400>,
620 <&cmu_top CLK_ACLK_CAM0_552>;
637 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
638 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
639 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
640 <&cmu_top CLK_ACLK_CAM1_333>,
641 <&cmu_top CLK_ACLK_CAM1_400>,
642 <&cmu_top CLK_ACLK_CAM1_552>;
656 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
657 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
658 <&cmu_top CLK_DIV_ACLK_IMEM_200>;