Lines Matching full:cmu_top
229 <&cmu_top CLK_MOUT_AUD_PLL>,
230 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
232 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
233 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
243 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
244 <&cmu_top CLK_DIV_SCLK_PCM1>,
245 <&cmu_top CLK_DIV_SCLK_I2S1>;
247 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_FOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
254 <&cmu_top CLK_SCLK_AUDIO0>;
263 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
264 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
271 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
272 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
273 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
275 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
276 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
288 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
289 <&cmu_top CLK_ACLK_GSCL_333>;
294 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
307 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
308 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
309 <&cmu_top CLK_SCLK_JPEG_MSCL>,
311 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
314 &cmu_top {
315 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
970 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
996 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
997 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
998 <&cmu_top CLK_MOUT_BUS_PLL_USER>;