dts/arm/rtsm_ve-aemv8a.dts

1 // SPDX-License-Identifier: GPL-2.0
5  * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 	interrupt-parent = <&gic>;
23 	#address-cells = <2>;
24 	#size-cells = <2>;
36 		#address-cells = <2>;
37 		#size-cells = <0>;
43 			enable-method = "spin-table";
44 			cpu-release-addr = <0x0 0x8000fff8>;
45 			next-level-cache = <&L2_0>;
51 			enable-method = "spin-table";
52 			cpu-release-addr = <0x0 0x8000fff8>;
53 			next-level-cache = <&L2_0>;
59 			enable-method = "spin-table";
60 			cpu-release-addr = <0x0 0x8000fff8>;
61 			next-level-cache = <&L2_0>;
67 			enable-method = "spin-table";
68 			cpu-release-addr = <0x0 0x8000fff8>;
69 			next-level-cache = <&L2_0>;
72 		L2_0: l2-cache0 {
74 			cache-level = <2>;
75 			cache-unified;
85 	reserved-memory {
86 		#address-cells = <2>;
87 		#size-cells = <2>;
93 			compatible = "shared-dma-pool";
95 			no-map;
99 	gic: interrupt-controller@2c001000 {  label
100 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
101 		#interrupt-cells = <3>;
102 		#address-cells = <0>;
103 		interrupt-controller;
112 		compatible = "arm,armv8-timer";
117 		clock-frequency = <100000000>;
121 		compatible = "arm,armv8-pmuv3";
129 		compatible = "arm,rtsm-display";
132 				remote-endpoint = <&clcd_pads>;
138 		#interrupt-cells = <1>;
139 		interrupt-map-mask = <0 0 63>;
140 		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
141 				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
142 				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
143 				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
144 				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
145 				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
146 				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
147 				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
148 				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
149 				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
150 				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
151 				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
152 				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
153 				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
154 				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
155 				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
156 				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
157 				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
158 				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
159 				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
160 				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
161 				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
162 				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
163 				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
164 				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
165 				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
166 				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
167 				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
168 				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
169 				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
170 				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
171 				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
172 				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
173 				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
174 				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
175 				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
176 				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
177 				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
178 				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
179 				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
180 				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
181 				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
182 				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;