Lines Matching +full:sun50i +full:- +full:h6 +full:- +full:ccu

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // based on the H6 dtsi, which is:
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
26 enable-method = "psci";
27 clocks = <&ccu CLK_CPUX>;
31 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 clocks = <&ccu CLK_CPUX>;
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 clocks = <&ccu CLK_CPUX>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 clocks = <&ccu CLK_CPUX>;
55 reserved-memory {
56 #address-cells = <2>;
57 #size-cells = <2>;
61 * 256 KiB reserved for Trusted Firmware-A (BL31).
67 no-map;
71 osc24M: osc24M-clk {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "osc24M";
79 compatible = "arm,cortex-a53-pmu";
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 compatible = "arm,psci-0.2";
93 compatible = "arm,armv8-timer";
94 arm,no-tick-in-suspend;
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
112 compatible = "allwinner,sun50i-h616-system-control";
114 #address-cells = <1>;
115 #size-cells = <1>;
119 compatible = "mmio-sram";
121 #address-cells = <1>;
122 #size-cells = <1>;
127 ccu: clock@3001000 { label
128 compatible = "allwinner,sun50i-h616-ccu";
131 clock-names = "hosc", "losc", "iosc";
132 #clock-cells = <1>;
133 #reset-cells = <1>;
137 compatible = "allwinner,sun50i-h616-wdt",
138 "allwinner,sun6i-a31-wdt";
145 compatible = "allwinner,sun50i-h616-pinctrl";
155 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
156 clock-names = "apb", "hosc", "losc";
157 gpio-controller;
158 #gpio-cells = <3>;
159 interrupt-controller;
160 #interrupt-cells = <3>;
162 ext_rgmii_pins: rgmii-pins {
168 drive-strength = <40>;
171 i2c0_pins: i2c0-pins {
176 i2c3_ph_pins: i2c3-ph-pins {
181 ir_rx_pin: ir-rx-pin {
186 mmc0_pins: mmc0-pins {
190 drive-strength = <30>;
191 bias-pull-up;
194 /omit-if-no-ref/
195 mmc1_pins: mmc1-pins {
199 drive-strength = <30>;
200 bias-pull-up;
203 mmc2_pins: mmc2-pins {
208 drive-strength = <30>;
209 bias-pull-up;
212 /omit-if-no-ref/
213 spi0_pins: spi0-pins {
218 /omit-if-no-ref/
219 spi0_cs0_pin: spi0-cs0-pin {
224 /omit-if-no-ref/
225 spi1_pins: spi1-pins {
230 /omit-if-no-ref/
231 spi1_cs0_pin: spi1-cs0-pin {
236 uart0_ph_pins: uart0-ph-pins {
241 /omit-if-no-ref/
242 uart1_pins: uart1-pins {
247 /omit-if-no-ref/
248 uart1_rts_cts_pins: uart1-rts-cts-pins {
254 gic: interrupt-controller@3021000 {
255 compatible = "arm,gic-400";
261 interrupt-controller;
262 #interrupt-cells = <3>;
266 compatible = "allwinner,sun50i-h616-mmc",
267 "allwinner,sun50i-a100-mmc";
269 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
270 clock-names = "ahb", "mmc";
271 resets = <&ccu RST_BUS_MMC0>;
272 reset-names = "ahb";
274 pinctrl-names = "default";
275 pinctrl-0 = <&mmc0_pins>;
277 max-frequency = <150000000>;
278 cap-sd-highspeed;
279 cap-mmc-highspeed;
280 mmc-ddr-3_3v;
281 cap-sdio-irq;
282 #address-cells = <1>;
283 #size-cells = <0>;
287 compatible = "allwinner,sun50i-h616-mmc",
288 "allwinner,sun50i-a100-mmc";
290 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
291 clock-names = "ahb", "mmc";
292 resets = <&ccu RST_BUS_MMC1>;
293 reset-names = "ahb";
295 pinctrl-names = "default";
296 pinctrl-0 = <&mmc1_pins>;
298 max-frequency = <150000000>;
299 cap-sd-highspeed;
300 cap-mmc-highspeed;
301 mmc-ddr-3_3v;
302 cap-sdio-irq;
303 #address-cells = <1>;
304 #size-cells = <0>;
308 compatible = "allwinner,sun50i-h616-emmc",
309 "allwinner,sun50i-a100-emmc";
311 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
312 clock-names = "ahb", "mmc";
313 resets = <&ccu RST_BUS_MMC2>;
314 reset-names = "ahb";
316 pinctrl-names = "default";
317 pinctrl-0 = <&mmc2_pins>;
319 max-frequency = <150000000>;
320 cap-sd-highspeed;
321 cap-mmc-highspeed;
322 mmc-ddr-3_3v;
323 cap-sdio-irq;
324 #address-cells = <1>;
325 #size-cells = <0>;
329 compatible = "snps,dw-apb-uart";
332 reg-shift = <2>;
333 reg-io-width = <4>;
334 clocks = <&ccu CLK_BUS_UART0>;
335 resets = <&ccu RST_BUS_UART0>;
340 compatible = "snps,dw-apb-uart";
343 reg-shift = <2>;
344 reg-io-width = <4>;
345 clocks = <&ccu CLK_BUS_UART1>;
346 resets = <&ccu RST_BUS_UART1>;
351 compatible = "snps,dw-apb-uart";
354 reg-shift = <2>;
355 reg-io-width = <4>;
356 clocks = <&ccu CLK_BUS_UART2>;
357 resets = <&ccu RST_BUS_UART2>;
362 compatible = "snps,dw-apb-uart";
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 clocks = <&ccu CLK_BUS_UART3>;
368 resets = <&ccu RST_BUS_UART3>;
373 compatible = "snps,dw-apb-uart";
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 clocks = <&ccu CLK_BUS_UART4>;
379 resets = <&ccu RST_BUS_UART4>;
384 compatible = "snps,dw-apb-uart";
387 reg-shift = <2>;
388 reg-io-width = <4>;
389 clocks = <&ccu CLK_BUS_UART5>;
390 resets = <&ccu RST_BUS_UART5>;
395 compatible = "allwinner,sun50i-h616-i2c",
396 "allwinner,sun8i-v536-i2c",
397 "allwinner,sun6i-a31-i2c";
400 clocks = <&ccu CLK_BUS_I2C0>;
401 resets = <&ccu RST_BUS_I2C0>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2c0_pins>;
405 #address-cells = <1>;
406 #size-cells = <0>;
410 compatible = "allwinner,sun50i-h616-i2c",
411 "allwinner,sun8i-v536-i2c",
412 "allwinner,sun6i-a31-i2c";
415 clocks = <&ccu CLK_BUS_I2C1>;
416 resets = <&ccu RST_BUS_I2C1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
423 compatible = "allwinner,sun50i-h616-i2c",
424 "allwinner,sun8i-v536-i2c",
425 "allwinner,sun6i-a31-i2c";
428 clocks = <&ccu CLK_BUS_I2C2>;
429 resets = <&ccu RST_BUS_I2C2>;
431 #address-cells = <1>;
432 #size-cells = <0>;
436 compatible = "allwinner,sun50i-h616-i2c",
437 "allwinner,sun8i-v536-i2c",
438 "allwinner,sun6i-a31-i2c";
441 clocks = <&ccu CLK_BUS_I2C3>;
442 resets = <&ccu RST_BUS_I2C3>;
444 #address-cells = <1>;
445 #size-cells = <0>;
449 compatible = "allwinner,sun50i-h616-i2c",
450 "allwinner,sun8i-v536-i2c",
451 "allwinner,sun6i-a31-i2c";
454 clocks = <&ccu CLK_BUS_I2C4>;
455 resets = <&ccu RST_BUS_I2C4>;
457 #address-cells = <1>;
458 #size-cells = <0>;
462 compatible = "allwinner,sun50i-h616-spi",
463 "allwinner,sun8i-h3-spi";
466 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
467 clock-names = "ahb", "mod";
468 resets = <&ccu RST_BUS_SPI0>;
470 #address-cells = <1>;
471 #size-cells = <0>;
475 compatible = "allwinner,sun50i-h616-spi",
476 "allwinner,sun8i-h3-spi";
479 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
480 clock-names = "ahb", "mod";
481 resets = <&ccu RST_BUS_SPI1>;
483 #address-cells = <1>;
484 #size-cells = <0>;
488 compatible = "allwinner,sun50i-h616-emac0",
489 "allwinner,sun50i-a64-emac";
492 interrupt-names = "macirq";
493 clocks = <&ccu CLK_BUS_EMAC0>;
494 clock-names = "stmmaceth";
495 resets = <&ccu RST_BUS_EMAC0>;
496 reset-names = "stmmaceth";
501 compatible = "snps,dwmac-mdio";
502 #address-cells = <1>;
503 #size-cells = <0>;
508 compatible = "allwinner,sun50i-h616-musb",
509 "allwinner,sun8i-h3-musb";
511 clocks = <&ccu CLK_BUS_OTG>;
512 resets = <&ccu RST_BUS_OTG>;
514 interrupt-names = "mc";
516 phy-names = "usb";
522 compatible = "allwinner,sun50i-h616-usb-phy";
528 reg-names = "phy_ctrl",
533 clocks = <&ccu CLK_USB_PHY0>,
534 <&ccu CLK_USB_PHY1>,
535 <&ccu CLK_USB_PHY2>,
536 <&ccu CLK_USB_PHY3>,
537 <&ccu CLK_BUS_EHCI2>;
538 clock-names = "usb0_phy",
543 resets = <&ccu RST_USB_PHY0>,
544 <&ccu RST_USB_PHY1>,
545 <&ccu RST_USB_PHY2>,
546 <&ccu RST_USB_PHY3>;
547 reset-names = "usb0_reset",
552 #phy-cells = <1>;
556 compatible = "allwinner,sun50i-h616-ehci",
557 "generic-ehci";
560 clocks = <&ccu CLK_BUS_OHCI0>,
561 <&ccu CLK_BUS_EHCI0>,
562 <&ccu CLK_USB_OHCI0>;
563 resets = <&ccu RST_BUS_OHCI0>,
564 <&ccu RST_BUS_EHCI0>;
566 phy-names = "usb";
571 compatible = "allwinner,sun50i-h616-ohci",
572 "generic-ohci";
575 clocks = <&ccu CLK_BUS_OHCI0>,
576 <&ccu CLK_USB_OHCI0>;
577 resets = <&ccu RST_BUS_OHCI0>;
579 phy-names = "usb";
584 compatible = "allwinner,sun50i-h616-ehci",
585 "generic-ehci";
588 clocks = <&ccu CLK_BUS_OHCI1>,
589 <&ccu CLK_BUS_EHCI1>,
590 <&ccu CLK_USB_OHCI1>;
591 resets = <&ccu RST_BUS_OHCI1>,
592 <&ccu RST_BUS_EHCI1>;
594 phy-names = "usb";
599 compatible = "allwinner,sun50i-h616-ohci",
600 "generic-ohci";
603 clocks = <&ccu CLK_BUS_OHCI1>,
604 <&ccu CLK_USB_OHCI1>;
605 resets = <&ccu RST_BUS_OHCI1>;
607 phy-names = "usb";
612 compatible = "allwinner,sun50i-h616-ehci",
613 "generic-ehci";
616 clocks = <&ccu CLK_BUS_OHCI2>,
617 <&ccu CLK_BUS_EHCI2>,
618 <&ccu CLK_USB_OHCI2>;
619 resets = <&ccu RST_BUS_OHCI2>,
620 <&ccu RST_BUS_EHCI2>;
622 phy-names = "usb";
627 compatible = "allwinner,sun50i-h616-ohci",
628 "generic-ohci";
631 clocks = <&ccu CLK_BUS_OHCI2>,
632 <&ccu CLK_USB_OHCI2>;
633 resets = <&ccu RST_BUS_OHCI2>;
635 phy-names = "usb";
640 compatible = "allwinner,sun50i-h616-ehci",
641 "generic-ehci";
644 clocks = <&ccu CLK_BUS_OHCI3>,
645 <&ccu CLK_BUS_EHCI3>,
646 <&ccu CLK_USB_OHCI3>;
647 resets = <&ccu RST_BUS_OHCI3>,
648 <&ccu RST_BUS_EHCI3>;
650 phy-names = "usb";
655 compatible = "allwinner,sun50i-h616-ohci",
656 "generic-ohci";
659 clocks = <&ccu CLK_BUS_OHCI3>,
660 <&ccu CLK_USB_OHCI3>;
661 resets = <&ccu RST_BUS_OHCI3>;
663 phy-names = "usb";
668 compatible = "allwinner,sun50i-h616-rtc";
672 <&ccu CLK_PLL_SYSTEM_32K>;
673 clock-names = "bus", "hosc",
674 "pll-32k";
675 #clock-cells = <1>;
679 compatible = "allwinner,sun50i-h616-r-ccu";
682 <&ccu CLK_PLL_PERIPH0>;
683 clock-names = "hosc", "losc", "iosc", "pll-periph";
684 #clock-cells = <1>;
685 #reset-cells = <1>;
689 compatible = "allwinner,sun50i-h616-r-pinctrl";
693 clock-names = "apb", "hosc", "losc";
694 gpio-controller;
695 #gpio-cells = <3>;
697 /omit-if-no-ref/
698 r_i2c_pins: r-i2c-pins {
703 r_rsb_pins: r-rsb-pins {
710 compatible = "allwinner,sun50i-h616-ir",
711 "allwinner,sun6i-a31-ir";
716 clock-names = "apb", "ir";
718 pinctrl-names = "default";
719 pinctrl-0 = <&ir_rx_pin>;
724 compatible = "allwinner,sun50i-h616-i2c",
725 "allwinner,sun8i-v536-i2c",
726 "allwinner,sun6i-a31-i2c";
732 #address-cells = <1>;
733 #size-cells = <0>;
737 compatible = "allwinner,sun50i-h616-rsb",
738 "allwinner,sun8i-a23-rsb";
742 clock-frequency = <3000000>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&r_rsb_pins>;
747 #address-cells = <1>;
748 #size-cells = <0>;