Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53";
28 enable-method = "psci";
29 clocks = <&ccu CLK_CPUX>;
30 clock-latency-ns = <244144>; /* 8 32k periods */
31 #cooling-cells = <2>;
35 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 clocks = <&ccu CLK_CPUX>;
40 clock-latency-ns = <244144>; /* 8 32k periods */
41 #cooling-cells = <2>;
45 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 clocks = <&ccu CLK_CPUX>;
50 clock-latency-ns = <244144>; /* 8 32k periods */
51 #cooling-cells = <2>;
55 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 clocks = <&ccu CLK_CPUX>;
60 clock-latency-ns = <244144>; /* 8 32k periods */
61 #cooling-cells = <2>;
65 de: display-engine {
66 compatible = "allwinner,sun50i-h6-display-engine";
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "osc24M";
79 compatible = "arm,cortex-a53-pmu";
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 compatible = "arm,psci-0.2";
93 compatible = "arm,armv8-timer";
94 arm,no-tick-in-suspend;
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
112 compatible = "allwinner,sun50i-h6-de3",
113 "allwinner,sun50i-a64-de2";
116 #address-cells = <1>;
117 #size-cells = <1>;
121 compatible = "allwinner,sun50i-h6-de3-clk";
123 clocks = <&ccu CLK_BUS_DE>,
124 <&ccu CLK_DE>;
125 clock-names = "bus",
127 resets = <&ccu RST_BUS_DE>;
128 #clock-cells = <1>;
129 #reset-cells = <1>;
133 compatible = "allwinner,sun50i-h6-de3-mixer-0";
137 clock-names = "bus",
143 #address-cells = <1>;
144 #size-cells = <0>;
150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
157 video-codec-g2@1c00000 {
158 compatible = "allwinner,sun50i-h6-vpu-g2";
161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
162 clock-names = "bus", "mod";
163 resets = <&ccu RST_BUS_VP9>;
167 video-codec@1c0e000 {
168 compatible = "allwinner,sun50i-h6-video-engine";
170 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
171 <&ccu CLK_MBUS_VE>;
172 clock-names = "ahb", "mod", "ram";
173 resets = <&ccu RST_BUS_VE>;
180 compatible = "allwinner,sun50i-h6-mali",
181 "arm,mali-t720";
186 interrupt-names = "job", "mmu", "gpu";
187 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
188 clock-names = "core", "bus";
189 resets = <&ccu RST_BUS_GPU>;
190 #cooling-cells = <2>;
195 compatible = "allwinner,sun50i-h6-crypto";
198 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
199 clock-names = "bus", "mod", "ram";
200 resets = <&ccu RST_BUS_CE>;
204 compatible = "allwinner,sun50i-h6-system-control",
205 "allwinner,sun50i-a64-system-control";
207 #address-cells = <1>;
208 #size-cells = <1>;
212 compatible = "mmio-sram";
214 #address-cells = <1>;
215 #size-cells = <1>;
218 de2_sram: sram-section@0 {
219 compatible = "allwinner,sun50i-h6-sram-c",
220 "allwinner,sun50i-a64-sram-c";
226 compatible = "mmio-sram";
228 #address-cells = <1>;
229 #size-cells = <1>;
232 ve_sram: sram-section@0 {
233 compatible = "allwinner,sun50i-h6-sram-c1",
234 "allwinner,sun4i-a10-sram-c1";
240 ccu: clock@3001000 { label
241 compatible = "allwinner,sun50i-h6-ccu";
244 clock-names = "hosc", "losc", "iosc";
245 #clock-cells = <1>;
246 #reset-cells = <1>;
249 dma: dma-controller@3002000 {
250 compatible = "allwinner,sun50i-h6-dma";
253 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
254 clock-names = "bus", "mbus";
255 dma-channels = <16>;
256 dma-requests = <46>;
257 resets = <&ccu RST_BUS_DMA>;
258 #dma-cells = <1>;
262 compatible = "allwinner,sun50i-h6-msgbox",
263 "allwinner,sun6i-a31-msgbox";
265 clocks = <&ccu CLK_BUS_MSGBOX>;
266 resets = <&ccu RST_BUS_MSGBOX>;
268 #mbox-cells = <1>;
272 compatible = "allwinner,sun50i-h6-sid";
274 #address-cells = <1>;
275 #size-cells = <1>;
277 ths_calibration: thermal-sensor-calibration@14 {
281 cpu_speed_grade: cpu-speed-grade@1c {
287 compatible = "allwinner,sun50i-h6-timer",
288 "allwinner,sun8i-a23-timer";
296 compatible = "allwinner,sun50i-h6-wdt",
297 "allwinner,sun6i-a31-wdt";
306 compatible = "allwinner,sun50i-h6-pwm";
308 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
309 clock-names = "mod", "bus";
310 resets = <&ccu RST_BUS_PWM>;
311 #pwm-cells = <3>;
316 compatible = "allwinner,sun50i-h6-pinctrl";
318 interrupt-parent = <&r_intc>;
323 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
324 clock-names = "apb", "hosc", "losc";
325 gpio-controller;
326 #gpio-cells = <3>;
327 interrupt-controller;
328 #interrupt-cells = <3>;
330 ext_rgmii_pins: rgmii-pins {
335 drive-strength = <40>;
338 hdmi_pins: hdmi-pins {
343 i2c0_pins: i2c0-pins {
348 i2c1_pins: i2c1-pins {
353 i2c2_pins: i2c2-pins {
358 mmc0_pins: mmc0-pins {
362 drive-strength = <30>;
363 bias-pull-up;
366 /omit-if-no-ref/
367 mmc1_pins: mmc1-pins {
371 drive-strength = <30>;
372 bias-pull-up;
375 mmc2_pins: mmc2-pins {
380 drive-strength = <30>;
381 bias-pull-up;
384 /omit-if-no-ref/
385 spi0_pins: spi0-pins {
390 /* pin shared with MMC2-CMD (eMMC) */
391 /omit-if-no-ref/
392 spi0_cs_pin: spi0-cs-pin {
397 /omit-if-no-ref/
398 spi1_pins: spi1-pins {
403 /omit-if-no-ref/
404 spi1_cs_pin: spi1-cs-pin {
409 /omit-if-no-ref/
410 spdif_tx_pin: spdif-tx-pin {
415 uart0_ph_pins: uart0-ph-pins {
420 uart1_pins: uart1-pins {
425 uart1_rts_cts_pins: uart1-rts-cts-pins {
431 gic: interrupt-controller@3021000 {
432 compatible = "arm,gic-400";
438 interrupt-controller;
439 #interrupt-cells = <3>;
443 compatible = "allwinner,sun50i-h6-iommu";
446 clocks = <&ccu CLK_BUS_IOMMU>;
447 resets = <&ccu RST_BUS_IOMMU>;
448 #iommu-cells = <1>;
452 compatible = "allwinner,sun50i-h6-mmc",
453 "allwinner,sun50i-a64-mmc";
455 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
456 clock-names = "ahb", "mmc";
457 resets = <&ccu RST_BUS_MMC0>;
458 reset-names = "ahb";
460 pinctrl-names = "default";
461 pinctrl-0 = <&mmc0_pins>;
462 max-frequency = <150000000>;
464 #address-cells = <1>;
465 #size-cells = <0>;
469 compatible = "allwinner,sun50i-h6-mmc",
470 "allwinner,sun50i-a64-mmc";
472 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
473 clock-names = "ahb", "mmc";
474 resets = <&ccu RST_BUS_MMC1>;
475 reset-names = "ahb";
477 pinctrl-names = "default";
478 pinctrl-0 = <&mmc1_pins>;
479 max-frequency = <150000000>;
481 #address-cells = <1>;
482 #size-cells = <0>;
486 compatible = "allwinner,sun50i-h6-emmc",
487 "allwinner,sun50i-a64-emmc";
489 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
490 clock-names = "ahb", "mmc";
491 resets = <&ccu RST_BUS_MMC2>;
492 reset-names = "ahb";
494 pinctrl-names = "default";
495 pinctrl-0 = <&mmc2_pins>;
496 max-frequency = <150000000>;
498 #address-cells = <1>;
499 #size-cells = <0>;
503 compatible = "snps,dw-apb-uart";
506 reg-shift = <2>;
507 reg-io-width = <4>;
508 clocks = <&ccu CLK_BUS_UART0>;
509 resets = <&ccu RST_BUS_UART0>;
514 compatible = "snps,dw-apb-uart";
517 reg-shift = <2>;
518 reg-io-width = <4>;
519 clocks = <&ccu CLK_BUS_UART1>;
520 resets = <&ccu RST_BUS_UART1>;
525 compatible = "snps,dw-apb-uart";
528 reg-shift = <2>;
529 reg-io-width = <4>;
530 clocks = <&ccu CLK_BUS_UART2>;
531 resets = <&ccu RST_BUS_UART2>;
536 compatible = "snps,dw-apb-uart";
539 reg-shift = <2>;
540 reg-io-width = <4>;
541 clocks = <&ccu CLK_BUS_UART3>;
542 resets = <&ccu RST_BUS_UART3>;
547 compatible = "allwinner,sun50i-h6-i2c",
548 "allwinner,sun6i-a31-i2c";
551 clocks = <&ccu CLK_BUS_I2C0>;
552 resets = <&ccu RST_BUS_I2C0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c0_pins>;
556 #address-cells = <1>;
557 #size-cells = <0>;
561 compatible = "allwinner,sun50i-h6-i2c",
562 "allwinner,sun6i-a31-i2c";
565 clocks = <&ccu CLK_BUS_I2C1>;
566 resets = <&ccu RST_BUS_I2C1>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c1_pins>;
570 #address-cells = <1>;
571 #size-cells = <0>;
575 compatible = "allwinner,sun50i-h6-i2c",
576 "allwinner,sun6i-a31-i2c";
579 clocks = <&ccu CLK_BUS_I2C2>;
580 resets = <&ccu RST_BUS_I2C2>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c2_pins>;
584 #address-cells = <1>;
585 #size-cells = <0>;
589 compatible = "allwinner,sun50i-h6-spi",
590 "allwinner,sun8i-h3-spi";
593 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
594 clock-names = "ahb", "mod";
596 dma-names = "rx", "tx";
597 resets = <&ccu RST_BUS_SPI0>;
599 #address-cells = <1>;
600 #size-cells = <0>;
604 compatible = "allwinner,sun50i-h6-spi",
605 "allwinner,sun8i-h3-spi";
608 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
609 clock-names = "ahb", "mod";
611 dma-names = "rx", "tx";
612 resets = <&ccu RST_BUS_SPI1>;
614 #address-cells = <1>;
615 #size-cells = <0>;
619 compatible = "allwinner,sun50i-h6-emac",
620 "allwinner,sun50i-a64-emac";
624 interrupt-names = "macirq";
625 resets = <&ccu RST_BUS_EMAC>;
626 reset-names = "stmmaceth";
627 clocks = <&ccu CLK_BUS_EMAC>;
628 clock-names = "stmmaceth";
632 compatible = "snps,dwmac-mdio";
633 #address-cells = <1>;
634 #size-cells = <0>;
639 #sound-dai-cells = <0>;
640 compatible = "allwinner,sun50i-h6-i2s";
643 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
644 clock-names = "apb", "mod";
646 resets = <&ccu RST_BUS_I2S1>;
647 dma-names = "rx", "tx";
652 #sound-dai-cells = <0>;
653 compatible = "allwinner,sun50i-h6-spdif";
656 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
657 clock-names = "apb", "spdif";
658 resets = <&ccu RST_BUS_SPDIF>;
660 dma-names = "rx", "tx";
665 compatible = "allwinner,sun50i-h6-musb",
666 "allwinner,sun8i-a33-musb";
668 clocks = <&ccu CLK_BUS_OTG>;
669 resets = <&ccu RST_BUS_OTG>;
671 interrupt-names = "mc";
673 phy-names = "usb";
679 compatible = "allwinner,sun50i-h6-usb-phy";
683 reg-names = "phy_ctrl",
686 clocks = <&ccu CLK_USB_PHY0>,
687 <&ccu CLK_USB_PHY3>;
688 clock-names = "usb0_phy",
690 resets = <&ccu RST_USB_PHY0>,
691 <&ccu RST_USB_PHY3>;
692 reset-names = "usb0_reset",
695 #phy-cells = <1>;
699 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
702 clocks = <&ccu CLK_BUS_OHCI0>,
703 <&ccu CLK_BUS_EHCI0>,
704 <&ccu CLK_USB_OHCI0>;
705 resets = <&ccu RST_BUS_OHCI0>,
706 <&ccu RST_BUS_EHCI0>;
708 phy-names = "usb";
713 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
716 clocks = <&ccu CLK_BUS_OHCI0>,
717 <&ccu CLK_USB_OHCI0>;
718 resets = <&ccu RST_BUS_OHCI0>;
720 phy-names = "usb";
728 clocks = <&ccu CLK_BUS_XHCI>,
729 <&ccu CLK_BUS_XHCI>,
731 clock-names = "ref", "bus_early", "suspend";
732 resets = <&ccu RST_BUS_XHCI>;
736 * to have a USB Type-B port routed to the port.
743 phy-names = "usb3-phy";
748 compatible = "allwinner,sun50i-h6-usb3-phy";
750 clocks = <&ccu CLK_USB_PHY1>;
751 resets = <&ccu RST_USB_PHY1>;
752 #phy-cells = <0>;
757 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
760 clocks = <&ccu CLK_BUS_OHCI3>,
761 <&ccu CLK_BUS_EHCI3>,
762 <&ccu CLK_USB_OHCI3>;
763 resets = <&ccu RST_BUS_OHCI3>,
764 <&ccu RST_BUS_EHCI3>;
766 phy-names = "usb";
771 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
774 clocks = <&ccu CLK_BUS_OHCI3>,
775 <&ccu CLK_USB_OHCI3>;
776 resets = <&ccu RST_BUS_OHCI3>;
778 phy-names = "usb";
783 compatible = "allwinner,sun50i-h6-dw-hdmi";
785 reg-io-width = <1>;
787 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
788 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
789 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
790 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
791 "hdcp-bus";
792 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
793 reset-names = "ctrl", "hdcp";
795 phy-names = "phy";
796 pinctrl-names = "default";
797 pinctrl-0 = <&hdmi_pins>;
801 #address-cells = <1>;
802 #size-cells = <0>;
808 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
818 hdmi_phy: hdmi-phy@6010000 {
819 compatible = "allwinner,sun50i-h6-hdmi-phy";
821 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
822 clock-names = "bus", "mod";
823 resets = <&ccu RST_BUS_HDMI>;
824 reset-names = "phy";
825 #phy-cells = <0>;
828 tcon_top: tcon-top@6510000 {
829 compatible = "allwinner,sun50i-h6-tcon-top";
831 clocks = <&ccu CLK_BUS_TCON_TOP>,
832 <&ccu CLK_TCON_TV0>;
833 clock-names = "bus",
834 "tcon-tv0";
835 clock-output-names = "tcon-top-tv0";
836 resets = <&ccu RST_BUS_TCON_TOP>;
837 #clock-cells = <1>;
840 #address-cells = <1>;
841 #size-cells = <0>;
844 #address-cells = <1>;
845 #size-cells = <0>;
850 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
855 #address-cells = <1>;
856 #size-cells = <0>;
861 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
866 #address-cells = <1>;
867 #size-cells = <0>;
872 remote-endpoint = <&tcon_tv_out_tcon_top>;
880 remote-endpoint = <&hdmi_in_tcon_top>;
886 tcon_tv: lcd-controller@6515000 {
887 compatible = "allwinner,sun50i-h6-tcon-tv",
888 "allwinner,sun8i-r40-tcon-tv";
891 clocks = <&ccu CLK_BUS_TCON_TV0>,
893 clock-names = "ahb",
894 "tcon-ch1";
895 resets = <&ccu RST_BUS_TCON_TV0>;
896 reset-names = "lcd";
899 #address-cells = <1>;
900 #size-cells = <0>;
906 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
911 #address-cells = <1>;
912 #size-cells = <0>;
917 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
924 compatible = "allwinner,sun50i-h6-rtc";
926 interrupt-parent = <&r_intc>;
929 clock-output-names = "osc32k", "osc32k-out", "iosc";
930 #clock-cells = <1>;
934 compatible = "allwinner,sun50i-h6-r-ccu";
937 <&ccu CLK_PLL_PERIPH0>;
938 clock-names = "hosc", "losc", "iosc", "pll-periph";
939 #clock-cells = <1>;
940 #reset-cells = <1>;
944 compatible = "allwinner,sun50i-h6-wdt",
945 "allwinner,sun6i-a31-wdt";
951 r_intc: interrupt-controller@7021000 {
952 compatible = "allwinner,sun50i-h6-r-intc";
953 interrupt-controller;
954 #interrupt-cells = <3>;
960 compatible = "allwinner,sun50i-h6-r-pinctrl";
962 interrupt-parent = <&r_intc>;
967 clock-names = "apb", "hosc", "losc";
968 gpio-controller;
969 #gpio-cells = <3>;
970 interrupt-controller;
971 #interrupt-cells = <3>;
973 r_i2c_pins: r-i2c-pins {
978 r_ir_rx_pin: r-ir-rx-pin {
983 r_rsb_pins: r-rsb-pins {
990 compatible = "allwinner,sun50i-h6-ir",
991 "allwinner,sun6i-a31-ir";
996 clock-names = "apb", "ir";
998 pinctrl-names = "default";
999 pinctrl-0 = <&r_ir_rx_pin>;
1004 compatible = "allwinner,sun50i-h6-i2c",
1005 "allwinner,sun6i-a31-i2c";
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&r_i2c_pins>;
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1018 compatible = "allwinner,sun8i-a23-rsb";
1022 clock-frequency = <3000000>;
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&r_rsb_pins>;
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1031 ths: thermal-sensor@5070400 {
1032 compatible = "allwinner,sun50i-h6-ths";
1035 clocks = <&ccu CLK_BUS_THS>;
1036 clock-names = "bus";
1037 resets = <&ccu RST_BUS_THS>;
1038 nvmem-cells = <&ths_calibration>;
1039 nvmem-cell-names = "calibration";
1040 #thermal-sensor-cells = <1>;
1044 thermal-zones {
1045 cpu-thermal {
1046 polling-delay-passive = <0>;
1047 polling-delay = <0>;
1048 thermal-sensors = <&ths 0>;
1051 cpu_alert: cpu-alert {
1057 cpu-crit {
1064 cooling-maps {
1067 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1075 gpu-thermal {
1076 polling-delay-passive = <1000>;
1077 polling-delay = <2000>;
1078 thermal-sensors = <&ths 1>;
1081 gpu_alert0: gpu-alert-0 {
1087 gpu_alert1: gpu-alert-1 {
1093 gpu_alert2: gpu-alert-2 {
1099 gpu-crit {
1106 cooling-maps {
1110 cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
1116 cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
1122 cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;