Lines Matching full:workaround
430 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
453 The workaround promotes data cache clean instructions to
455 Please note that this does not necessarily enable the workaround,
475 The workaround promotes data cache clean instructions to
477 Please note that this does not necessarily enable the workaround,
498 The workaround promotes data cache clean instructions to
501 workaround, as it depends on the alternative framework, which will
520 The workaround promotes data cache clean instructions to
522 Please note that this does not necessarily enable the workaround,
538 The workaround is to promote device loads to use Load-Acquire
540 Please note that this does not necessarily enable the workaround,
559 The workaround is to verify that the Stage 1 translation
561 Please note that this does not necessarily enable the workaround,
573 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
596 The workaround is to write the contextidr_el1 register on exception
598 Please note that this does not necessarily enable the workaround,
622 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
626 without a break-before-make. The workaround is to disable the usage
637 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
654 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
680 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
696 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
713 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
722 workaround repeats the TLBI+DSB operation.
728 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
743 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
746 This option adds a workaround for ARM Neoverse-N1 erratum
750 modified by another CPU. The workaround depends on a firmware
753 Workaround the issue by hiding the DIC feature from EL0. This
759 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
762 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
766 non-cacheable memory attributes. The workaround depends on a firmware
769 KVM guests must also have the workaround implemented or they can
785 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
787 hardware update of the page table's dirty bit. The workaround
793 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
796 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
813 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
823 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
828 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
841 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
846 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
862 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
866 Enable workaround for ARM Cortex-A710 erratum 2054223
872 Workaround is to issue two TSB consecutively on affected cores.
877 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
881 Enable workaround for ARM Neoverse-N2 erratum 2067961
887 Workaround is to issue two TSB consecutively on affected cores.
895 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
900 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
913 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
918 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
935 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
948 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
952 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
966 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
970 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
989 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
993 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1007 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1011 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1024 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1027 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1034 mprotect() system call. Workaround the problem by doing a break-before-make
1043 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1047 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1057 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1061 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1071 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1074 This option adds the workaround for the following errata:
1114 Enable workaround for errata 22375 and 24313.
1193 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1203 The workaround is to ensure these bits are clear in TCR_ELx.
1204 The workaround only affects the Fujitsu-A64FX.
1281 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"