Lines Matching +full:cross +full:- +full:arm64 +full:- +full:system
1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64 config
260 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
301 # VA_BITS - PAGE_SHIFT - 3
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
411 source "arch/arm64/Kconfig.platforms"
432 at stage-2.
440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
451 system can deadlock.
454 data cache clean-and-invalidate.
462 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
467 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
476 data cache clean-and-invalidate.
484 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
489 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
492 If a Cortex-A53 processor is executing a store or prefetch for
499 data cache clean-and-invalidate.
507 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
512 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
521 data cache clean-and-invalidate.
529 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
533 erratum 832075 on Cortex-A57 parts up to r1p2.
535 Affected Cortex-A57 parts might deadlock when exclusive load/store
536 instructions to Write-Back memory are mixed with Device loads.
538 The workaround is to promote device loads to use Load-Acquire
547 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
552 erratum 834220 on Cortex-A57 parts up to r1p2.
554 Affected Cortex-A57 parts might report a Stage 2 translation
568 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
572 This option removes the AES hwcap for aarch32 user-space to
573 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
584 bool "Cortex-A53: 845719: a load might read incorrect data"
589 erratum 845719 on Cortex-A53 parts up to r0p4.
591 When running a compat (AArch32) userspace on an affected Cortex-A53
597 return to a 32-bit task.
605 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
608 This option links the kernel with '--fix-cortex-a53-843419' and
611 Cortex-A53 parts up to r0p4.
616 def_bool $(ld-option,--fix-cortex-a53-843419)
619 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
622 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
624 Affected Cortex-A55 cores (all revisions) could cause incorrect
626 without a break-before-make. The workaround is to disable the usage
633 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
637 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
640 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
650 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
654 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
656 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
663 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
667 This option adds work arounds for ARM Cortex-A57 erratum 1319537
670 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
676 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
680 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
682 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
692 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
696 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
698 Under very rare circumstances, affected Cortex-A55 CPUs
699 may not handle a race between a break-before-make sequence on one
709 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
713 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
715 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
719 break-before-make sequence, then under very rare circumstances
725 bool "Cortex-A76: Software Step might prevent interrupt recognition"
728 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
730 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
731 of a system call instruction (SVC) can prevent recognition of
733 exception handler of the system call and either kernel debugging
737 when handling a system call from a task that is being stepped
743 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
746 This option adds a workaround for ARM Neoverse-N1 erratum
749 Affected Neoverse-N1 cores could execute a stale instruction when
754 forces user-space to perform cache maintenance.
759 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
762 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
764 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
765 of a store-exclusive or read of PAR_EL1 and a load with device or
766 non-cacheable memory attributes. The workaround depends on a firmware
770 deadlock the system.
782 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
785 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
786 Affected Cortex-A510 might not respect the ordering rules for
793 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
796 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
797 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
805 previous guest entry, and can be restored from the in-memory copy.
810 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
813 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
814 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
818 user-space should not be using these instructions.
823 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
828 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
830 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
841 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
846 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
848 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
862 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
866 Enable workaround for ARM Cortex-A710 erratum 2054223
877 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
881 Enable workaround for ARM Neoverse-N2 erratum 2067961
895 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
900 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
902 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
913 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
918 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
920 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
931 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
935 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
937 Under very rare circumstances, affected Cortex-A510 CPUs
938 may not handle a race between a break-before-make sequence on one
948 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
952 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
954 Affected Cortex-A510 core might fail to write into system registers after the
960 is stopped and before performing a system register write to one of the affected
966 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
970 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
972 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
989 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
993 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
995 Affected Cortex-A510 core might cause trace data corruption, when being written
1007 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1011 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1014 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1024 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1027 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1029 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1030 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1033 Only user-space does executable to non-executable permission transition via
1034 mprotect() system call. Workaround the problem by doing a break-before-make
1043 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1047 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1049 On an affected Cortex-A520 core, a speculatively executed unprivileged
1057 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1061 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1063 On an affected Cortex-A510 core, a speculatively executed unprivileged
1071 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1076 * ARM Cortex-A76 erratum 3324349
1077 * ARM Cortex-A77 erratum 3324348
1078 * ARM Cortex-A78 erratum 3324344
1079 * ARM Cortex-A78C erratum 3324346
1080 * ARM Cortex-A78C erratum 3324347
1081 * ARM Cortex-A710 erratam 3324338
1082 * ARM Cortex-A715 errartum 3456084
1083 * ARM Cortex-A720 erratum 3456091
1084 * ARM Cortex-A725 erratum 3456106
1085 * ARM Cortex-X1 erratum 3324344
1086 * ARM Cortex-X1C erratum 3324346
1087 * ARM Cortex-X2 erratum 3324338
1088 * ARM Cortex-X3 erratum 3324335
1089 * ARM Cortex-X4 erratum 3194386
1090 * ARM Cortex-X925 erratum 3324334
1091 * ARM Neoverse-N1 erratum 3324349
1093 * ARM Neoverse-N3 erratum 3456111
1094 * ARM Neoverse-V1 erratum 3324341
1096 * ARM Neoverse-V3 erratum 3312417
1104 SSBS. The presence of the SSBS special-purpose register is hidden
1116 This implements two gicv3-its errata workarounds for ThunderX. Both
1128 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1132 ITS SYNC command hang for cross node io and collections/cpu mapping.
1156 contains data for a non-current ASID. The fix is to
1167 interrupts in host. Trapping both GICv3 group-0 and group-1
1190 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1193 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1194 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1198 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1199 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1200 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1201 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1204 The workaround only affects the Fujitsu-A64FX.
1264 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1274 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1281 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1285 MSI doorbell writes with non-zero values for the device ID.
1305 The system will use 16KB pages support. AArch32 emulation
1314 look-up. AArch32 emulation requires applications compiled
1330 bool "36-bit" if EXPERT
1334 bool "39-bit"
1338 bool "42-bit"
1342 bool "47-bit"
1346 bool "48-bit"
1349 bool "52-bit"
1352 Enable 52-bit virtual addressing for userspace when explicitly
1353 requested via a hint to mmap(). The kernel will also use 52-bit
1355 this feature is available, otherwise it reverts to 48-bit).
1357 NOTE: Enabling 52-bit virtual addressing in conjunction with
1360 impact on its susceptibility to brute-force attacks.
1362 If unsure, select 48-bit virtual addressing instead.
1367 bool "Force 52-bit virtual addresses for userspace"
1370 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1371 to maintain compatibility with older software by providing 48-bit VAs
1374 This configuration option disables the 48-bit compatibility logic, and
1375 forces all userspace addresses to be 52-bit on HW that supports it. One
1396 bool "48-bit"
1399 bool "52-bit (ARMv8.2)"
1403 Enable support for a 52-bit physical address space, introduced as
1404 part of the ARMv8.2-LPA extension.
1407 do not support ARMv8.2-LPA, but with some added memory overhead (and
1426 bool "Build big-endian kernel"
1428 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1431 Say Y if you plan on running a kernel with a big-endian userspace.
1434 bool "Build little-endian kernel"
1436 Say Y if you plan on running a kernel with a little-endian userspace.
1437 This is usually the case for distributions targeting arm64.
1442 bool "Multi-core scheduler support"
1444 Multi-core scheduler support improves the CPU scheduler's decision
1445 making when dealing with multi-core CPU chips at a cost of slightly
1454 by sharing mid-level caches, last-level cache tags or internal
1465 int "Maximum number of CPUs (2-4096)"
1470 bool "Support for hot-pluggable CPUs"
1474 can be controlled through /sys/devices/system/cpu.
1487 Enable NUMA (Non-Uniform Memory Access) support.
1500 system. Increases memory reserved to accommodate various tables.
1515 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1567 bool "Xen guest support on ARM64"
1568 depends on ARM64 && OF
1572 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1578 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1581 # ----+-------------------+--------------+-----------------+--------------------+
1609 Speculation attacks against some high-performance processors can
1621 Speculation attacks against some high-performance processors can
1623 When taking an exception from user-space, a sequence of branches
1630 Apply read-only attributes of VM areas to the linear alias of
1631 the backing pages as well. This prevents code or read-only data
1644 user-space memory directly by pointing TTBR0_EL1 to a reserved
1654 to system calls as pointer arguments. For details, see
1655 Documentation/arch/arm64/tagged-address-abi.rst.
1658 bool "Kernel support for 32-bit EL0"
1664 This option enables support for a 32-bit EL0 running under a 64-bit
1665 kernel at EL1. AArch32-specific components such as system calls,
1673 If you want to execute 32-bit userspace applications, say Y.
1678 bool "Enable kuser helpers page for 32-bit applications"
1681 Warning: disabling this option may break 32-bit user programs.
1686 the system. This permits binaries to be run on ARMv4 through
1705 bool "Enable vDSO for 32-bit applications"
1711 Place in the process address space of 32-bit applications an
1715 You must have a 32-bit build of glibc 2.22 or later for programs
1719 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1723 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1724 otherwise with '-marm'.
1727 bool "Fix up misaligned multi-word loads and stores in user space"
1760 monitor to maintain update atomicity. If your system does not
1769 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1770 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1785 The SETEND instruction alters the data-endianness of the
1792 Note: All the cpus on the system must have mixed endian support at EL0
1793 for this feature to be enabled. If a new CPU - which doesn't support mixed
1794 endian - is hotplugged in after this feature has been enabled, there could
1813 Similarly, writes to read-only pages with the DBM bit set will
1814 clear the read-only bit (AP[2]) instead of raising a
1818 to work on pre-ARMv8.1 hardware and the performance impact is
1826 prevents the kernel or hypervisor from accessing user-space (EL0)
1836 def_bool $(as-instr,.arch_extension lse)
1847 As part of the Large System Extensions, ARMv8.1 introduces new
1851 Say Y here to make use of these instructions for the in-kernel
1862 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1865 def_bool $(as-instr,.arch armv8.2-a+sha3)
1877 DC CVAP itself if the system does not define a point of persistence).
1887 On CPUs with these extensions system software can use additional
1892 and access the new registers if the system supports the extension.
1925 context-switched along with the process.
1934 but with the feature disabled. On such a system, this option should
1948 If the compiler supports the -mbranch-protection or
1949 -msign-return-address flag (e.g. GCC 7 or later), then this option
1960 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1964 def_bool $(cc-option,-msign-return-address=all)
1967 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1970 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1973 def_bool $(as-instr,.arch_extension rcpc)
2003 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2010 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2021 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2055 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2061 is enabled and the system supports BTI all kernel code including
2066 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2082 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2086 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2101 architectural support for run-time, always-on detection of
2103 to eliminate vulnerabilities arising from memory-unsafe
2111 not be allowed a late bring-up.
2117 Documentation/arch/arm64/memory-tagging-extension.rst.
2129 Access Never to be used with Execute-only mappings.
2160 If you need the kernel to boot on SVE-capable hardware with broken
2179 bool "Support for NMI-like interrupts"
2182 Adds support for mimicking Non-Maskable Interrupts through the use of
2225 random u64 value in /chosen/kaslr-seed at kernel entry.
2252 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2272 bool "Enable support for the ARM64 ACPI parking protocol"
2275 Enable support for the ARM64 ACPI parking protocol. If disabled
2276 the kernel will not allow booting through the ARM64 ACPI parking
2284 Provide a set of default command-line options at build time by
2298 Uses the command-line options passed by the boot loader. If
2308 command-line options your boot loader passes to the kernel.
2330 by UEFI firmware (such as non-volatile variables, realtime
2344 continue to boot on existing non-UEFI platforms.
2375 source "arch/arm64/kvm/Kconfig"