Kconfig - OpenGrok cross reference for /openbmc/linux/arch/arm64/Kconfig

424 	  The affected design reports FEAT_HAFDBS as not implemented in
457 	  the kernel if an affected CPU is detected.
479 	  the kernel if an affected CPU is detected.
502 	  only patch the kernel if an affected CPU is detected.
524 	  the kernel if an affected CPU is detected.
535 	  Affected Cortex-A57 parts might deadlock when exclusive load/store
542 	  the kernel if an affected CPU is detected.
554 	  Affected Cortex-A57 parts might report a Stage 2 translation
563 	  the kernel if an affected CPU is detected.
575 	  Affected parts may corrupt the AES state if an interrupt is
591 	  When running a compat (AArch32) userspace on an affected Cortex-A53
600 	  the kernel if an affected CPU is detected.
624 	  Affected Cortex-A55 cores (all revisions) could cause incorrect
627 	  of hardware DBM locally on the affected cores. CPUs not affected by
640 	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
656 	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
682 	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
692 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
698 	  Under very rare circumstances, affected Cortex-A55 CPUs
703 	  Work around this by adding the affected CPUs to the list that needs
715 	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
730 	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
749 	  Affected Neoverse-N1 cores could execute a stale instruction when
764 	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
786 	  Affected Cortex-A510 might not respect the ordering rules for
788 	  is to not enable the feature on affected CPUs.
797 	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
814 	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
830 	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
848 	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
868 	  Affected cores may fail to flush the trace data on a TSB instruction, when
872 	  Workaround is to issue two TSB consecutively on affected cores.
883 	  Affected cores may fail to flush the trace data on a TSB instruction, when
887 	  Workaround is to issue two TSB consecutively on affected cores.
902 	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
920 	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
931 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
937 	  Under very rare circumstances, affected Cortex-A510 CPUs
942 	  Work around this by adding the affected CPUs to the list that needs
954 	  Affected Cortex-A510 core might fail to write into system registers after the
960 	  is stopped and before performing a system register write to one of the affected
972 	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
995 	  Affected Cortex-A510 core might cause trace data corruption, when being written
1000 	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
1014 	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1017 	  Work around this problem by returning 0 when reading the affected counter in
1019 	  is the same to firmware disabling affected counters.
1049 	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1063 	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1098 	  On affected cores "MSR SSBS, #0" instructions may not affect