Lines Matching +full:0 +full:x0007b000
22 #define TTB_C (1 << 0)
25 #define TTB_RGN_NC (0 << 3)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 bic r0, r0, #0x1000 @ ...i............
43 bic r0, r0, #0x0006 @ .............ca.
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
60 bic r1, r1, #0x1 @ ...............m
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
62 mov r1, #0
63 mcr p15, 0, r1, c7, c5, 4 @ ISB
76 mov r1, #0
77 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
100 mov r2, #0
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
108 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
109 bic r2, r2, #0xff @ extract the PID
110 and r1, r1, #0xff
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
141 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
143 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
144 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
146 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
147 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
148 mrc p15, 0, r9, c1, c0, 0 @ control register
154 mov ip, #0
155 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
156 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
158 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
159 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
161 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
163 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
166 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
167 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
168 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
170 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
171 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
172 mcr p15, 0, ip, c7, c5, 4 @ ISB
199 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
201 orr r0, r0, #0x20
202 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
206 mov r0, #0
207 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
208 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
209 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
211 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
212 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
217 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
219 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
224 mrc p15, 0, r0, c1, c0, 0 @ read control register
235 ldr r6, =0x4107b362 @ id for ARM1136 r0p2
236 mrc p15, 0, r5, c0, c0, 0 @ get processor id
238 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
240 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
249 * 0 110 0011 1.00 .111 1101 < we want
253 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
273 .long 0x0007b000
274 .long 0x0007f000