Lines Matching +full:5 +full:d
30 * the cache line size of the I and D cache
49 mov r2, #(16 << 5)
57 sub r2, r2, #(1 << 5)
91 .align 5
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 .align 5
137 .align 5
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
156 subs r1, r1, #(1 << 5) @ next set
175 .align 5
181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
204 .align 5
220 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
232 * Ensure no D cache aliasing occurs, either with itself or
238 .align 5
241 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
250 .align 5
256 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
257 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
277 .align 5
281 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
283 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
284 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
291 .align 5
295 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
297 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
302 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
303 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
317 .align 5
320 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
327 .align 5
334 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
335 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
348 .align 5
351 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
358 .align 5
365 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
366 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
436 .align 5
443 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
466 .align 5
483 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
494 .align 5
499 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
523 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
524 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
537 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
540 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4