arm/mm/proc-arm922.S

60 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
63 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
79 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
80 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
82 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
84 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
87 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
97 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
110 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
134 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
140 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
141 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
160 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
162 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
167 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
195 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
196 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
200 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
215 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
220 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
221 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
240 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
242 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
243 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
247 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
262 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
266 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
279 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
283 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
320 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
341 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
349 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
355 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
356 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
357 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
358 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
372 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
373 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
380 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
381 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
383 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
387 	mrc	p15, 0, r0, c1, c0		@ get control register v4