1 // SPDX-License-Identifier: GPL-2.0-only
3  * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
17 #define CACHE_WAY_PER_SET	8
19 #define CACHE_WAY_SIZE(l2ctype)	(8192 << (((l2ctype) >> 8) & 0xf))
44 	int set, way;  in xsc3_l2_inv_all()  local
49 		for (way = 0; way < CACHE_WAY_PER_SET; way++) {  in xsc3_l2_inv_all()
50 			set_way = (way << 29) | (set << 5);  in xsc3_l2_inv_all()
61 	if (va != -1)  in l2_unmap_va()
70 	unsigned long pa_offset = pa << (32 - PAGE_SHIFT);  in l2_map_va()
71 	if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {  in l2_map_va()
80 	return va + (pa_offset >> (32 - PAGE_SHIFT));  in l2_map_va()
90 	if (start == 0 && end == -1ul) {  in xsc3_l2_inv_range()
95 	vaddr = -1;  /* to force the first mapping */  in xsc3_l2_inv_range()
100 	if (start & (CACHE_LINE_SIZE - 1)) {  in xsc3_l2_inv_range()
101 		vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);  in xsc3_l2_inv_range()
104 		start = (start | (CACHE_LINE_SIZE - 1)) + 1;  in xsc3_l2_inv_range()
110 	while (start < (end & ~(CACHE_LINE_SIZE - 1))) {  in xsc3_l2_inv_range()
134 	vaddr = -1;  /* to force the first mapping */  in xsc3_l2_clean_range()
136 	start &= ~(CACHE_LINE_SIZE - 1);  in xsc3_l2_clean_range()
149  * optimize L2 flush all operation by set/way format
154 	int set, way;  in xsc3_l2_flush_all()  local
159 		for (way = 0; way < CACHE_WAY_PER_SET; way++) {  in xsc3_l2_flush_all()
160 			set_way = (way << 29) | (set << 5);  in xsc3_l2_flush_all()
172 	if (start == 0 && end == -1ul) {  in xsc3_l2_flush_range()
177 	vaddr = -1;  /* to force the first mapping */  in xsc3_l2_flush_range()
179 	start &= ~(CACHE_LINE_SIZE - 1);  in xsc3_l2_flush_range()