Lines Matching refs:a
107 The ARM922T is a version of the ARM920T, but with smaller
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
146 This is a variant of the ARM920. It has slightly different
165 The FA526 is a version of the ARMv4 compatible processor with
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
201 ARM946E-S is a member of the ARM9E-S family of high-
222 with an addition of a floating-point unit.
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
637 and to handle IO-space as a special type of memory by assigning
638 manager or client roles to running code (such as a process).
689 The Thumb instruction set is a compressed form of the standard ARM
697 If you don't know what this all is, saying Y is a safe choice.
703 Say Y here if you have a CPU with the ThumbEE extension and code to
738 on an external transaction monitoring block called a global
740 implement a global monitor, this option can cause programs that
752 Say Y if you plan on running a kernel in little-endian mode.
760 Say Y if you plan on running a kernel in big-endian mode.
799 you have a reason not to or are unsure, say N.
806 LITTLE and big cores. Say Y here to enable a workaround for
814 you have a reason not to or are unsure, say N.
826 If your SoC is configured to have a different size, define the value
860 on being able to manipulate the branch predictor for a victim
880 taking an exception, a sequence of branches overwrites the branch
887 An SMP system using a pre-ARMv6 processor (there are apparently
888 a few prototypes like that in existence) and therefore access to
902 helper code to userspace in read only form at a fixed location
916 such exploits. However, in that case, if a binary or library
917 relying on those helpers is run, it will receive a SIGILL signal,
966 The outer cache has a outer_cache_fns.sync function pointer
995 This option should be selected by machines which have a L2x0
1004 inadvertently configuring a broken kernel.
1029 They are architecturally defined to behave as the execution of a
1033 as clean lines are not invalidated as a result of these operations.
1042 PL310 treats a cacheable write transaction during a Clean &
1067 This option adds a write barrier to the cpu_idle loop so that,