arm/mach-tegra/sleep-tegra30.S

592 	.word	TEGRA_EMC_BASE + EMC_CFG				@0x0
593 	.word	TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
594 	.word	TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
595 	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL			@0xc
596 	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
597 	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
598 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
599 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
603 	.word	TEGRA_EMC0_BASE + EMC_CFG				@0x0
604 	.word	TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL			@0x4
605 	.word	TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
606 	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL			@0xc
607 	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
608 	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
609 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
610 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
611 	.word	TEGRA_EMC1_BASE + EMC_CFG				@0x20
612 	.word	TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL			@0x24
613 	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28
614 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
615 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
619 	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
620 	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
621 	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
622 	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
623 	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
624 	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
625 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
626 	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
630 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
633 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
642 	.word	0x0