1386 #define MDCNFG_PrChrg(Tcpu)     	/*  Pre-Charge time [2..32 Tcpu]   */ \  argument
1387                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1388 #define MDCNFG_CeilPrChrg(Tcpu) 	/*  Ceil. of PrChrg [2..32 Tcpu]   */ \  argument
1389                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1391 #define MDCNFG_Ref(Tcpu)        	/*  Refresh time [2..32 Tcpu]      */ \  argument
1392                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1393 #define MDCNFG_CeilRef(Tcpu)    	/*  Ceil. of Ref [2..32 Tcpu]      */ \  argument
1394                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1396 #define MDCNFG_DataLtch(Tcpu)   	/*  Data Latch delay [0..3 Tcpu]   */ \  argument
1397                 	((Tcpu) << FShft (MDCNFG_TDL))
1400 #define MDCNFG_RefInt(Tcpu)     	/*  min. Refresh Interval          */ \  argument
1402                 	((Tcpu)/8 << FShft (MDCNFG_DRI))
1468 #define MSC_1stRdAcc(Tcpu)      	/*  1st Read Access time (burst    */ \  argument
1470                 	((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1471 #define MSC_Ceil1stRdAcc(Tcpu)  	/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \  argument
1472                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1473 #define MSC_RdAcc(Tcpu)	        	/*  Read Access time (non-burst    */ \  argument
1475                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1476 #define MSC_CeilRdAcc(Tcpu)     	/*  Ceil. of RdAcc [2..64 Tcpu]    */ \  argument
1477                 	((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1480 #define MSC_NxtRdAcc(Tcpu)      	/*  Next Read Access time (burst   */ \  argument
1482                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1483 #define MSC_CeilNxtRdAcc(Tcpu)  	/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \  argument
1484                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1485 #define MSC_WrAcc(Tcpu)	        	/*  Write Access time (non-burst   */ \  argument
1487                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1488 #define MSC_CeilWrAcc(Tcpu)     	/*  Ceil. of WrAcc [2..64 Tcpu]    */ \  argument
1489                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1492 #define MSC_Rec(Tcpu)	        	/*  Recovery time [0..28 Tcpu]     */ \  argument
1493                 	(((Tcpu)/4) << FShft (MSC_RRR))
1494 #define MSC_CeilRec(Tcpu)       	/*  Ceil. of Rec [0..28 Tcpu]      */ \  argument
1495                 	((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1521 #define MECR_IOClk(Tcpu)        	/*  I/O Clock [2..64 Tcpu]         */ \  argument
1522                 	((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1523 #define MECR_CeilIOClk(Tcpu)    	/*  Ceil. of IOClk [2..64 Tcpu]    */ \  argument
1524                 	((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1527 #define MECR_AttrClk(Tcpu)      	/*  Attribute Clock [2..64 Tcpu]   */ \  argument
1528                 	((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1529 #define MECR_CeilAttrClk(Tcpu)  	/*  Ceil. of AttrClk [2..64 Tcpu]  */ \  argument
1530                 	((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1532 #define MECR_MemClk(Tcpu)       	/*  Memory Clock [2..64 Tcpu]      */ \  argument
1533                 	((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1534 #define MECR_CeilMemClk(Tcpu)   	/*  Ceil. of MemClk [2..64 Tcpu]   */ \  argument
1535                 	((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1687 #define LCCR0_DMADel(Tcpu)      	/*  palette DMA request Delay      */ \  argument
1689                 	((Tcpu)/2 << FShft (LCCR0_PDD))