Lines Matching +full:gpo +full:- +full:config +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
44 int shift = off * 2; in samsung_gpio_setpull_updown()
58 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
59 int shift = off * 2; in samsung_gpio_getpull_updown()
71 void __iomem *reg = chip->base; in samsung_gpio_setcfg_2bit()
72 unsigned int shift = off * 2; in samsung_gpio_setcfg_2bit()
78 return -EINVAL; in samsung_gpio_setcfg_2bit()
92 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
106 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
107 con >>= off * 2; in samsung_gpio_getcfg_2bit()
115 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
134 void __iomem *reg = chip->base; in samsung_gpio_setcfg_4bit()
138 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_setcfg_4bit()
139 reg -= 4; in samsung_gpio_setcfg_4bit()
155 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
169 void __iomem *reg = chip->base; in samsung_gpio_getcfg_4bit()
173 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_getcfg_4bit()
174 reg -= 4; in samsung_gpio_getcfg_4bit()
187 for (; nr_chips > 0; nr_chips--, chipcfg++) { in samsung_gpiolib_set_cfg()
188 if (!chipcfg->set_config) in samsung_gpiolib_set_cfg()
189 chipcfg->set_config = samsung_gpio_setcfg_4bit; in samsung_gpiolib_set_cfg()
190 if (!chipcfg->get_config) in samsung_gpiolib_set_cfg()
191 chipcfg->get_config = samsung_gpio_getcfg_4bit; in samsung_gpiolib_set_cfg()
192 if (!chipcfg->set_pull) in samsung_gpiolib_set_cfg()
193 chipcfg->set_pull = samsung_gpio_setpull_updown; in samsung_gpiolib_set_cfg()
194 if (!chipcfg->get_pull) in samsung_gpiolib_set_cfg()
195 chipcfg->get_pull = samsung_gpio_getpull_updown; in samsung_gpiolib_set_cfg()
206 [2] = {
238 * base + 0x00: Control register, 2 bits per gpio
239 * gpio n: 2 bits starting at (2*n)
240 * 00 = input, 01 = output, others mean special-function
248 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_input()
255 con &= ~(3 << (offset * 2)); in samsung_gpiolib_2bit_input()
267 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_output()
281 con &= ~(3 << (offset * 2)); in samsung_gpiolib_2bit_output()
282 con |= 1 << (offset * 2); in samsung_gpiolib_2bit_output()
298 * 0000 = input, 0001 = output, others mean special-function
311 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_input()
315 if (ourchip->bitmap_gpio_int & BIT(offset)) in samsung_gpiolib_4bit_input()
330 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_output()
364 * 0000 = input, 0001 = output, others mean special-function
367 * 0000 = input, 0001 = output, others mean special-function
373 * the data register at ourchip->base + 0x04.
380 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_input()
385 offset -= 8; in samsung_gpiolib_4bit2_input()
387 regcon -= 4; in samsung_gpiolib_4bit2_input()
402 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_output()
409 con_offset -= 8; in samsung_gpiolib_4bit2_output()
411 regcon -= 4; in samsung_gpiolib_4bit2_output()
437 void __iomem *base = ourchip->base; in samsung_gpiolib_set()
457 val = __raw_readl(ourchip->base + 0x04); in samsung_gpiolib_get()
484 gpn = chip->chip.base; in s3c_gpiolib_track()
485 for (i = 0; i < chip->chip.ngpio; i++, gpn++) { in s3c_gpiolib_track()
493 * samsung_gpiolib_add() - add the Samsung gpio_chip.
504 struct gpio_chip *gc = &chip->chip; in samsung_gpiolib_add()
507 BUG_ON(!chip->base); in samsung_gpiolib_add()
508 BUG_ON(!gc->label); in samsung_gpiolib_add()
509 BUG_ON(!gc->ngpio); in samsung_gpiolib_add()
511 spin_lock_init(&chip->lock); in samsung_gpiolib_add()
513 if (!gc->direction_input) in samsung_gpiolib_add()
514 gc->direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add()
515 if (!gc->direction_output) in samsung_gpiolib_add()
516 gc->direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add()
517 if (!gc->set) in samsung_gpiolib_add()
518 gc->set = samsung_gpiolib_set; in samsung_gpiolib_add()
519 if (!gc->get) in samsung_gpiolib_add()
520 gc->get = samsung_gpiolib_get; in samsung_gpiolib_add()
523 if (chip->pm != NULL) { in samsung_gpiolib_add()
524 if (!chip->pm->save || !chip->pm->resume) in samsung_gpiolib_add()
526 gc->label); in samsung_gpiolib_add()
528 pr_err("gpio: %s has no PM function\n", gc->label); in samsung_gpiolib_add()
544 chip->chip.direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add_2bit_chips()
545 chip->chip.direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add_2bit_chips()
547 if (!chip->config) in samsung_gpiolib_add_2bit_chips()
548 chip->config = &samsung_gpio_cfgs[7]; in samsung_gpiolib_add_2bit_chips()
549 if (!chip->pm) in samsung_gpiolib_add_2bit_chips()
550 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); in samsung_gpiolib_add_2bit_chips()
551 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_2bit_chips()
552 chip->base = base + ((i) * offset); in samsung_gpiolib_add_2bit_chips()
559 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
580 chip->chip.direction_input = samsung_gpiolib_4bit_input; in samsung_gpiolib_add_4bit_chips()
581 chip->chip.direction_output = samsung_gpiolib_4bit_output; in samsung_gpiolib_add_4bit_chips()
583 if (!chip->config) in samsung_gpiolib_add_4bit_chips()
584 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit_chips()
585 if (!chip->pm) in samsung_gpiolib_add_4bit_chips()
586 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit_chips()
587 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_4bit_chips()
588 chip->base = base + ((i) * 0x20); in samsung_gpiolib_add_4bit_chips()
590 chip->bitmap_gpio_int = 0; in samsung_gpiolib_add_4bit_chips()
599 for (; nr_chips > 0; nr_chips--, chip++) { in samsung_gpiolib_add_4bit2_chips()
600 chip->chip.direction_input = samsung_gpiolib_4bit2_input; in samsung_gpiolib_add_4bit2_chips()
601 chip->chip.direction_output = samsung_gpiolib_4bit2_output; in samsung_gpiolib_add_4bit2_chips()
603 if (!chip->config) in samsung_gpiolib_add_4bit2_chips()
604 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit2_chips()
605 if (!chip->pm) in samsung_gpiolib_add_4bit2_chips()
606 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit2_chips()
616 return samsung_chip->irq_base + offset; in samsung_gpiolib_to_irq()
621 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; in s3c64xx_gpiolib_mbank_to_irq()
626 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; in s3c64xx_gpiolib_lbank_to_irq()
635 * C 8 4Bit Yes 2
638 * F 16 2Bit Yes 4 [1]
640 * H 10 4Bit[2] Yes 6
641 * I 16 2Bit Yes None
642 * J 12 2Bit Yes None
643 * K 16 4Bit[2] No None
644 * L 15 4Bit[2] No None
646 * N 16 2Bit No IRQ_EINT
647 * O 16 2Bit Yes 7
648 * P 15 2Bit Yes 8
649 * Q 9 2Bit Yes 9
652 * [2] BANK has two control registers, GPxCON0 and GPxCON1
681 .config = &samsung_gpio_cfgs[0],
696 .config = &samsung_gpio_cfgs[1],
716 .config = &samsung_gpio_cfgs[0],
724 .config = &samsung_gpio_cfgs[1],
737 .config = &samsung_gpio_cfgs[6],
744 .config = &samsung_gpio_cfgs[7],
751 .config = &samsung_gpio_cfgs[7],
758 .config = &samsung_gpio_cfgs[6],
762 .label = "GPO",
765 .config = &samsung_gpio_cfgs[6],
772 .config = &samsung_gpio_cfgs[6],
781 .config = &samsung_gpio_cfgs[5],
797 * pinctrl-samsung driver is used, providing both GPIO and pin control in samsung_gpiolib_init()
798 * interfaces. For legacy (non-DT) platforms this driver is used. in samsung_gpiolib_init()
820 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) in s3c_gpio_cfgpin() argument
828 return -EINVAL; in s3c_gpio_cfgpin()
830 offset = pin - chip->chip.base; in s3c_gpio_cfgpin()
833 ret = samsung_gpio_do_setcfg(chip, offset, config); in s3c_gpio_cfgpin()
845 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgpin_range()
860 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgall_range()
878 return -EINVAL; in s3c_gpio_setpull()
880 offset = pin - chip->chip.base; in s3c_gpio_setpull()