1 // SPDX-License-Identifier: GPL-2.0-only
3  * OMAP MPUSS low power code
8  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
9  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
11  * CPU0, CPU1 and MPUSS each have there own power domain and
12  * hence multiple low power combinations of MPUSS are possible.
17  * to the Cortex-A9 processor must be asserted by the external
18  * power controller.
21  * below modes are supported from power gain vs latency point of view.
24  *	----------------------------------------------
30  *	----------------------------------------------
32  * Note: CPU0 is the master core and it is the last CPU to go down
33  * and first to wake-up when MPUSS low power states are excercised
48 #include <asm/hardware/cache-l2x0.h>
53 #include "omap4-sar-layout.h"
60 #include "prm-regbits-44xx.h"
75  * struct cpu_pm_ops - CPU pm operations
76  * @finish_suspend:	CPU suspend finisher function pointer
77  * @resume:		CPU resume function pointer
78  * @scu_prepare:	CPU Snoop Control program function pointer
79  * @hotplug_restart:	CPU restart function pointer
81  * Structure holds functions pointer for CPU low power operations like
122 	if (pm_info->wkup_sar_addr)  in set_cpu_wakeup_addr()
123 		writel_relaxed(addr, pm_info->wkup_sar_addr);  in set_cpu_wakeup_addr()
127  * Store the SCU power status value to scratchpad memory
148 	if (pm_info->scu_sar_addr)  in scu_pwrst_prepare()
149 		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);  in scu_pwrst_prepare()
181  * Store the CPU cluster state for L2X0 low power operations.
187 	if (pm_info->l2x0_sar_addr)  in l2x0_pwrst_prepare()
188 		writel_relaxed(save_state, pm_info->l2x0_sar_addr);  in l2x0_pwrst_prepare()
213  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
214  * The purpose of this function is to manage low power programming
216  * @cpu : CPU ID
217  * @power_state: Low power state.
222  *	0 - Nothing lost and no need to save: MPUSS INACTIVE
223  *	1 - CPUx L1 and logic lost: MPUSS CSWR
224  *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
225  *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
227 __cpuidle int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state,  in omap4_enter_lowpower()  argument
230 	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);  in omap4_enter_lowpower()
234 		return -ENXIO;  in omap4_enter_lowpower()
257 		return -ENXIO;  in omap4_enter_lowpower()
263 	 * Check MPUSS next state and save interrupt controller if needed.  in omap4_enter_lowpower()
264 	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.  in omap4_enter_lowpower()
271 	cpu_clear_prev_logic_pwrst(cpu);  in omap4_enter_lowpower()
272 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_enter_lowpower()
273 	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);  in omap4_enter_lowpower()
278 	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));  in omap4_enter_lowpower()
279 	omap_pm_ops.scu_prepare(cpu, power_state);  in omap4_enter_lowpower()
280 	l2x0_pwrst_prepare(cpu, save_state);  in omap4_enter_lowpower()
283 	 * Call low level function  with targeted low power state.  in omap4_enter_lowpower()
290 	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)  in omap4_enter_lowpower()
297 	 * Restore the CPUx power state to ON otherwise CPUx  in omap4_enter_lowpower()
298 	 * power domain can transitions to programmed low power  in omap4_enter_lowpower()
303 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_enter_lowpower()
311  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
312  * @cpu : CPU ID
313  * @power_state: CPU low power state.
315 int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)  in omap4_hotplug_cpu()  argument
317 	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);  in omap4_hotplug_cpu()
321 		return -ENXIO;  in omap4_hotplug_cpu()
323 	/* Use the achievable power state for the domain */  in omap4_hotplug_cpu()
324 	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,  in omap4_hotplug_cpu()
330 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_hotplug_cpu()
331 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_hotplug_cpu()
332 	set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));  in omap4_hotplug_cpu()
333 	omap_pm_ops.scu_prepare(cpu, power_state);  in omap4_hotplug_cpu()
336 	 * CPU never retuns back if targeted power state is OFF mode.  in omap4_hotplug_cpu()
337 	 * CPU ONLINE follows normal CPU ONLINE ptah via  in omap4_hotplug_cpu()
342 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_hotplug_cpu()
370 		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");  in omap4_mpuss_init()
371 		return -ENODEV;  in omap4_mpuss_init()
374 	/* Initilaise per CPU PM information */  in omap4_mpuss_init()
377 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;  in omap4_mpuss_init()
379 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
382 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
384 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;  in omap4_mpuss_init()
386 	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");  in omap4_mpuss_init()
387 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
389 		return -ENODEV;  in omap4_mpuss_init()
392 	/* Clear CPU previous power domain state */  in omap4_mpuss_init()
393 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
396 	/* Initialise CPU0 power domain state to ON */  in omap4_mpuss_init()
397 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
401 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;  in omap4_mpuss_init()
403 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
406 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
408 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;  in omap4_mpuss_init()
411 	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");  in omap4_mpuss_init()
412 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
414 		return -ENODEV;  in omap4_mpuss_init()
417 	/* Clear CPU previous power domain state */  in omap4_mpuss_init()
418 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
421 	/* Initialise CPU1 power domain state to ON */  in omap4_mpuss_init()
422 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
426 		pr_err("Failed to lookup MPUSS power domain\n");  in omap4_mpuss_init()
427 		return -ENODEV;  in omap4_mpuss_init()