Lines Matching refs:MV78XX0_REGS_VIRT_BASE

49 #define MV78XX0_REGS_VIRT_BASE		IOMEM(0xfec00000)  macro
73 #define DDR_VIRT_BASE		(MV78XX0_REGS_VIRT_BASE + 0x00000)
80 #define DEV_BUS_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x10000)
98 #define PCIE00_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x40000)
99 #define PCIE01_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x44000)
100 #define PCIE02_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x48000)
101 #define PCIE03_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x4c000)
112 #define PCIE10_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x80000)
113 #define PCIE11_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x84000)
114 #define PCIE12_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x88000)
115 #define PCIE13_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x8c000)