47 static void __iomem *avic_base;  variable
60 		irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);  in avic_set_irq_fiq()
61 		imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);  in avic_set_irq_fiq()
64 		irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);  in avic_set_irq_fiq()
65 		imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);  in avic_set_irq_fiq()
88 	avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);  in avic_irq_suspend()
89 	imx_writel(gc->wake_active, avic_base + ct->regs.mask);  in avic_irq_suspend()
110 	imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);  in avic_irq_resume()
130 	gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,  in avic_init_gc()
153 		nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;  in avic_handle_irq()
172 	avic_base = irqbase;  in mxc_init_irq()
189 	imx_writel(0, avic_base + AVIC_INTCNTL);  in mxc_init_irq()
190 	imx_writel(0x1f, avic_base + AVIC_NIMASK);  in mxc_init_irq()
193 	imx_writel(0, avic_base + AVIC_INTENABLEH);  in mxc_init_irq()
194 	imx_writel(0, avic_base + AVIC_INTENABLEL);  in mxc_init_irq()
197 	imx_writel(0, avic_base + AVIC_INTTYPEH);  in mxc_init_irq()
198 	imx_writel(0, avic_base + AVIC_INTTYPEL);  in mxc_init_irq()
213 		imx_writel(0, avic_base + AVIC_NIPRIORITY(i));  in mxc_init_irq()
228 	void __iomem *avic_base;  in imx_avic_init()  local
230 	avic_base = of_iomap(node, 0);  in imx_avic_init()
231 	BUG_ON(!avic_base);  in imx_avic_init()
232 	mxc_init_irq(avic_base);  in imx_avic_init()