Lines Matching refs:tmp1
23 tmp1 .req r4 label
85 mcr p15, 0, tmp1, c7, c0, 4
137 ldr tmp1, [r2, #UDDRC_PCTRL_0]
138 bic tmp1, tmp1, #0x1
139 str tmp1, [r2, #UDDRC_PCTRL_0]
141 ldr tmp1, [r2, #UDDRC_PCTRL_1]
142 bic tmp1, tmp1, #0x1
143 str tmp1, [r2, #UDDRC_PCTRL_1]
145 ldr tmp1, [r2, #UDDRC_PCTRL_2]
146 bic tmp1, tmp1, #0x1
147 str tmp1, [r2, #UDDRC_PCTRL_2]
149 ldr tmp1, [r2, #UDDRC_PCTRL_3]
150 bic tmp1, tmp1, #0x1
151 str tmp1, [r2, #UDDRC_PCTRL_3]
153 ldr tmp1, [r2, #UDDRC_PCTRL_4]
154 bic tmp1, tmp1, #0x1
155 str tmp1, [r2, #UDDRC_PCTRL_4]
159 ldr tmp1, [r2, #UDDRC_PSTAT]
161 tst tmp1, tmp2
165 ldr tmp1, [r2, #UDDRC_PWRCTL]
166 orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
167 str tmp1, [r2, #UDDRC_PWRCTL]
171 ldr tmp1, [r2, #UDDRC_STAT]
172 bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
173 cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
181 ldr tmp1, [r3, DDR3PHY_ACDLLCR]
182 bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
183 str tmp1, [r3, DDR3PHY_ACDLLCR]
186 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
187 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
188 str tmp1, [r3, #DDR3PHY_DX0DLLCR]
190 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
191 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
192 str tmp1, [r3, #DDR3PHY_DX1DLLCR]
196 ldr tmp1, [r3, #DDR3PHY_DXCCR]
197 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
198 str tmp1, [r3, #DDR3PHY_DXCCR]
201 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
202 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
203 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
204 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
205 str tmp1, [r3, #DDR3PHY_ACIOCR]
208 ldr tmp1, [r3, #DDR3PHY_DSGCR]
209 orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
210 str tmp1, [r3, #DDR3PHY_DSGCR]
223 ldr tmp1, [r3, #DDR3PHY_DXCCR]
224 bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
225 str tmp1, [r3, #DDR3PHY_DXCCR]
228 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
229 bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
230 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
231 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
232 str tmp1, [r3, #DDR3PHY_ACIOCR]
235 ldr tmp1, [r3, #DDR3PHY_DSGCR]
236 bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
237 str tmp1, [r3, #DDR3PHY_DSGCR]
240 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
241 bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
242 str tmp1, [r3, #DDR3PHY_DX0DLLCR]
244 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
245 bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
246 str tmp1, [r3, #DDR3PHY_DX1DLLCR]
249 mov tmp1, #0
250 str tmp1, [r2, #UDDRC_SWCTRL]
253 ldr tmp1, [r2, #UDDRC_DFIMISC]
254 bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
255 str tmp1, [r2, #UDDRC_DFIMISC]
258 mov tmp1, #UDDRC_SWCTRL_SW_DONE
259 str tmp1, [r2, #UDDRC_SWCTRL]
262 ldr tmp1, [r2, #UDDRC_SWSTAT]
263 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
267 mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
269 str tmp1, [r3, #DDR3PHY_PIR]
273 ldr tmp1, [r3, #DDR3PHY_PGSR]
274 tst tmp1, #DDR3PHY_PGSR_IDONE
278 mov tmp1, #0
279 str tmp1, [r2, #UDDRC_SWCTRL]
282 ldr tmp1, [r2, #UDDRC_DFIMISC]
283 orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
284 str tmp1, [r2, #UDDRC_DFIMISC]
287 mov tmp1, #UDDRC_SWCTRL_SW_DONE
288 str tmp1, [r2, #UDDRC_SWCTRL]
292 ldr tmp1, [r2, #UDDRC_SWSTAT]
293 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
297 ldr tmp1, [r2, #UDDRC_PWRCTL]
298 bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
299 str tmp1, [r2, #UDDRC_PWRCTL]
303 ldr tmp1, [r2, #UDDRC_STAT]
304 bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
305 cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
309 ldr tmp1, [r2, #UDDRC_PCTRL_0]
310 orr tmp1, tmp1, #0x1
311 str tmp1, [r2, #UDDRC_PCTRL_0]
313 ldr tmp1, [r2, #UDDRC_PCTRL_1]
314 orr tmp1, tmp1, #0x1
315 str tmp1, [r2, #UDDRC_PCTRL_1]
317 ldr tmp1, [r2, #UDDRC_PCTRL_2]
318 orr tmp1, tmp1, #0x1
319 str tmp1, [r2, #UDDRC_PCTRL_2]
321 ldr tmp1, [r2, #UDDRC_PCTRL_3]
322 orr tmp1, tmp1, #0x1
323 str tmp1, [r2, #UDDRC_PCTRL_3]
325 ldr tmp1, [r2, #UDDRC_PCTRL_4]
326 orr tmp1, tmp1, #0x1
327 str tmp1, [r2, #UDDRC_PCTRL_4]
485 ldr tmp1, [pmc, tmp3]
486 bic tmp1, tmp1, #AT91_PMC_PRES
487 orr tmp1, tmp1, #AT91_PMC_PRES_64
488 str tmp1, [pmc, tmp3]
496 ldr tmp1, [pmc, #AT91_CKGR_MOR]
497 bic tmp1, tmp1, #AT91_PMC_MOSCEN
498 orr tmp1, tmp1, #AT91_PMC_KEY
499 str tmp1, [pmc, #AT91_CKGR_MOR]
502 ldr tmp1, [pmc, #AT91_PMC_SR]
503 str tmp1, .saved_osc_status
504 tst tmp1, #AT91_PMC_MOSCRCS
508 ldr tmp1, [pmc, #AT91_CKGR_MOR]
509 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
510 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
511 orr tmp1, tmp1, #AT91_PMC_KEY
512 str tmp1, [pmc, #AT91_CKGR_MOR]
515 2: ldr tmp1, [pmc, #AT91_PMC_SR]
516 tst tmp1, #AT91_PMC_MOSCRCS
528 ldr tmp1, [pmc, tmp3]
529 bic tmp1, tmp1, #AT91_PMC_PRES
530 str tmp1, [pmc, tmp3]
537 ldr tmp1, .saved_osc_status
538 tst tmp1, #AT91_PMC_MOSCRCS
542 ldr tmp1, [pmc, #AT91_CKGR_MOR]
543 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
544 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
545 orr tmp1, tmp1, #AT91_PMC_KEY
546 str tmp1, [pmc, #AT91_CKGR_MOR]
549 3: ldr tmp1, [pmc, #AT91_PMC_SR]
550 tst tmp1, #AT91_PMC_MOSCRCS
554 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
555 orr tmp1, tmp1, #AT91_PMC_MOSCEN
556 orr tmp1, tmp1, #AT91_PMC_KEY
557 str tmp1, [pmc, #AT91_CKGR_MOR]
573 ldr tmp1, [pmc, #AT91_PMC_SR]
574 str tmp1, .saved_osc_status
575 tst tmp1, #AT91_PMC_MOSCRCS
579 ldr tmp1, [pmc, #AT91_CKGR_MOR]
580 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
581 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
582 orr tmp1, tmp1, #AT91_PMC_KEY
583 str tmp1, [pmc, #AT91_CKGR_MOR]
586 1: ldr tmp1, [pmc, #AT91_PMC_SR]
587 tst tmp1, #AT91_PMC_MOSCRCS
591 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
592 bic tmp1, tmp1, #AT91_PMC_MOSCSEL
593 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
594 orr tmp1, tmp1, #AT91_PMC_KEY
595 str tmp1, [pmc, #AT91_CKGR_MOR]
600 ldr tmp1, [pmc, #AT91_CKGR_MOR]
601 bic tmp1, tmp1, #AT91_PMC_MOSCEN
602 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
603 orr tmp1, tmp1, #AT91_PMC_KEY
604 str tmp1, [pmc, #AT91_CKGR_MOR]
607 ldr tmp1, [pmc, tmp2]
608 bic tmp1, tmp1, #AT91_PMC_CSS
609 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
610 str tmp1, [pmc, tmp2]
615 ldr tmp1, [pmc, #AT91_CKGR_MOR]
616 orr tmp1, tmp1, #AT91_PMC_WAITMODE
617 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
618 orr tmp1, tmp1, #AT91_PMC_KEY
619 str tmp1, [pmc, #AT91_CKGR_MOR]
628 ldr tmp1, [pmc, #AT91_CKGR_MOR]
629 orr tmp1, tmp1, #AT91_PMC_MOSCEN
630 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
631 orr tmp1, tmp1, #AT91_PMC_KEY
632 str tmp1, [pmc, #AT91_CKGR_MOR]
637 ldr tmp1, [pmc, tmp2]
638 bic tmp1, tmp1, #AT91_PMC_CSS
639 str tmp1, [pmc, tmp2]
644 ldr tmp1, [pmc, #AT91_CKGR_MOR]
645 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
646 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
647 orr tmp1, tmp1, #AT91_PMC_KEY
648 str tmp1, [pmc, #AT91_CKGR_MOR]
653 ldr tmp1, [pmc, tmp2]
654 bic tmp1, tmp1, #AT91_PMC_CSS
655 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
656 str tmp1, [pmc, tmp2]
661 ldr tmp1, .saved_osc_status
662 tst tmp1, #AT91_PMC_MOSCRCS
666 ldr tmp1, [pmc, #AT91_CKGR_MOR]
667 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
668 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
669 orr tmp1, tmp1, #AT91_PMC_KEY
670 str tmp1, [pmc, #AT91_CKGR_MOR]
673 4: ldr tmp1, [pmc, #AT91_PMC_SR]
674 tst tmp1, #AT91_PMC_MOSCRCS
682 ldr tmp1, .pmc_version
683 cmp tmp1, #AT91_PMC_V1
693 mov tmp1, #0
696 orr tmp1, tmp1, tmp2
701 orr tmp1, tmp1, tmp2
702 str tmp1, .saved_pllar
705 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
706 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
707 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
708 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
711 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
712 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
713 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
714 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
717 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
718 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
719 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
720 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
723 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
724 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
725 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
728 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
729 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
730 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
731 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
737 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
738 str tmp1, .saved_pllar
741 mov tmp1, #AT91_PMC_PLLCOUNT
742 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
743 str tmp1, [pmc, #AT91_CKGR_PLLAR]
755 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
756 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
757 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
758 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
761 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
762 str tmp1, [pmc, #AT91_PMC_PLL_ACR]
765 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
768 orr tmp1, tmp1, tmp3
769 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
772 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
773 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
774 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
775 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
778 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
779 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
780 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
781 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
782 bic tmp1, tmp1, #0xff
785 orr tmp1, tmp1, tmp3
786 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
789 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
790 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
791 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
792 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
795 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
796 tst tmp1, #0x1
810 1: ldr tmp1, [pmc, #AT91_PMC_SR]
811 tst tmp1, #AT91_PMC_LOCKA
826 mov tmp1, #1
827 e_loop: cmp tmp1, #5
831 str tmp1, [pmc, #AT91_PMC_MCR_V2]
835 cmp tmp1, #1
841 cmp tmp1, #2
847 cmp tmp1, #3
863 wait_mckrdy tmp1
865 add tmp1, tmp1, #1
882 mov tmp1, #1
883 r_loop: cmp tmp1, #5
887 cmp tmp1, #1
893 cmp tmp1, #2
899 cmp tmp1, #3
909 str tmp1, [pmc, #AT91_PMC_MCR_V2]
917 orr tmp3, tmp3, tmp1
921 wait_mckrdy tmp1
923 add tmp1, tmp1, #1
937 ldr tmp1, [pmc, tmp2]
938 str tmp1, .saved_mckr
945 bic tmp1, tmp1, #AT91_PMC_CSS
948 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
950 str tmp1, [pmc, tmp2]
982 ldr tmp1, .mckr_offset
984 str tmp2, [pmc, tmp1]
996 ldr tmp1, [pmc, tmp2]
997 bic tmp1, tmp1, #AT91_PMC_CSS
998 str tmp1, [pmc, tmp2]
1005 mov tmp1, #0x1
1006 str tmp1, [r0, #0x10]
1009 1: ldr tmp1, [r0, #0x10]
1010 tst tmp1, #0x1
1015 mov tmp1, #0xA5000000
1016 add tmp1, tmp1, #0x1
1017 at91_backup_set_lpm tmp1
1018 str tmp1, [r0, #0]
1033 mov tmp1, #0
1034 mcr p15, 0, tmp1, c7, c10, 4
1040 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1041 str tmp1, .mckr_offset
1042 ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
1043 str tmp1, .pmc_version
1044 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
1045 str tmp1, .memtype
1046 ldr tmp1, [r0, #PM_DATA_MODE]
1047 str tmp1, .pm_mode
1053 ldr tmp1, [r0, #PM_DATA_PMC]
1054 str tmp1, .pmc_base
1055 cmp tmp1, #0
1056 ldrne tmp2, [tmp1, #0]
1058 ldr tmp1, [r0, #PM_DATA_RAMC0]
1059 str tmp1, .sramc_base
1060 cmp tmp1, #0
1061 ldrne tmp2, [tmp1, #0]
1063 ldr tmp1, [r0, #PM_DATA_RAMC1]
1064 str tmp1, .sramc1_base
1065 cmp tmp1, #0
1066 ldrne tmp2, [tmp1, #0]
1070 ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
1071 str tmp1, .sramc_phy_base
1072 cmp tmp1, #0
1073 ldrne tmp2, [tmp1, #0]
1075 ldr tmp1, [r0, #PM_DATA_SHDWC]
1076 str tmp1, .shdwc
1077 cmp tmp1, #0
1078 ldrne tmp2, [tmp1, #0]
1080 ldr tmp1, [r0, #PM_DATA_SFRBU]
1081 str tmp1, .sfrbu
1082 cmp tmp1, #0
1083 ldrne tmp2, [tmp1, #0x10]