Lines Matching +full:0 +full:x00000017
37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
50 * Use 0 here to get code right that creates a userspace
53 #define USR_MODE 0x00000000
54 #define SVC_MODE 0x00000000
56 #define USR_MODE 0x00000010
57 #define SVC_MODE 0x00000013
59 #define FIQ_MODE 0x00000011
60 #define IRQ_MODE 0x00000012
61 #define MON_MODE 0x00000016
62 #define ABT_MODE 0x00000017
63 #define HYP_MODE 0x0000001a
64 #define UND_MODE 0x0000001b
65 #define SYSTEM_MODE 0x0000001f
66 #define MODE32_BIT 0x00000010
67 #define MODE_MASK 0x0000001f
69 #define V4_PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */
70 #define V7M_PSR_T_BIT 0x01000000
78 #define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */
79 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */
80 #define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */
81 #define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */
82 #define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */
83 #define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */
84 #define PSR_V_BIT 0x10000000
85 #define PSR_C_BIT 0x20000000
86 #define PSR_Z_BIT 0x40000000
87 #define PSR_N_BIT 0x80000000
92 #define PSR_f 0xff000000 /* Flags */
93 #define PSR_s 0x00ff0000 /* Status */
94 #define PSR_x 0x0000ff00 /* Extension */
95 #define PSR_c 0x000000ff /* Control */
100 #define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
101 #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
102 #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
103 #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
111 #define PSR_ENDSTATE 0
118 #define PT_TEXT_ADDR 0x10000
119 #define PT_DATA_ADDR 0x10004
120 #define PT_TEXT_END_ADDR 0x10008
151 #define ARM_r0 uregs[0]