Lines Matching full:rp
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
47 ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
49 ldr rp, [rp, #0] ; \
51 tst rp, #(1 << bit) ; \
55 ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
57 ldr rp, [rp, #0] ; \
59 tst rp, #(1 << bit) ; \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
67 .macro addruart, rp, rv, tmp
68 adr \rp, 99f @ actual addr of 99f
69 ldr \rv, [\rp] @ linked addr is stored there
70 sub \rv, \rv, \rp @ offset between the two
71 ldr \rp, [\rp, #4] @ linked tegra_uart_config
72 sub \tmp, \rp, \rv @ actual tegra_uart_config
73 ldr \rp, [\tmp] @ Load tegra_uart_config
74 cmp \rp, #1 @ needs initialization?
81 10: ldr \rp, =TEGRA_PMC_SCRATCH20
82 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
83 lsr \rv, \rp, #18 @ 19:18 are console type
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
107 20: checkuart(\rp, \rv, L, 6, A)
113 21: checkuart(\rp, \rv, L, 7, B)
119 22: checkuart(\rp, \rv, H, 23, C)
125 23: checkuart(\rp, \rv, U, 1, D)
132 checkuart(\rp, \rv, U, 2, E)
136 90: mov \rp, #0
140 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
141 cmp \rp, #0 @ Valid UART address?
143 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
145 92: and \rv, \rp, #0xffffff @ offset within 1MB section
183 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys