include/asm/v7m.h

1 /* SPDX-License-Identifier: GPL-2.0 */
49  * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50  * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
62 /* Memory-mapped MPU registers for M-class */
75 #define PMSAv8_RBAR_A(n)	(PMSAv8_RBAR + 8*(n))
76 #define PMSAv8_RLAR_A(n)	(PMSAv8_RLAR + 8*(n))
81 #define	V7M_SCB_ICIALLU		0x250	/* I-cache invalidate all to PoU */
82 #define	V7M_SCB_ICIMVAU		0x258	/* I-cache invalidate by MVA to PoU */
83 #define	V7M_SCB_DCIMVAC		0x25c	/* D-cache invalidate by MVA to PoC */
84 #define	V7M_SCB_DCISW		0x260	/* D-cache invalidate by set-way */
85 #define	V7M_SCB_DCCMVAU		0x264	/* D-cache clean by MVA to PoU */
86 #define	V7M_SCB_DCCMVAC		0x268	/* D-cache clean by MVA to PoC */
87 #define	V7M_SCB_DCCSW		0x26c	/* D-cache clean by set-way */
88 #define	V7M_SCB_DCCIMVAC	0x270	/* D-cache clean and invalidate by MVA to PoC */
89 #define	V7M_SCB_DCCISW		0x274	/* D-cache clean and invalidate by set-way */
90 #define	V7M_SCB_BPIALL		0x278	/* D-cache clean and invalidate by set-way */