Lines Matching +full:omap +full:- +full:mailbox
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a15";
52 operating-points = <
59 clock-names = "cpu";
61 clock-latency = <300000>; /* From omap-cpufreq driver */
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
71 operating-points = <
78 clock-names = "cpu";
80 clock-latency = <300000>; /* From omap-cpufreq driver */
83 #cooling-cells = <2>; /* min followed by max */
87 thermal-zones {
88 #include "omap4-cpu-thermal.dtsi"
89 #include "omap5-gpu-thermal.dtsi"
90 #include "omap5-core-thermal.dtsi"
94 compatible = "arm,armv7-timer";
100 interrupt-parent = <&gic>;
104 compatible = "arm,cortex-a15-pmu";
111 * interconnect as simple-pm-bus probes at module_init() time.
114 compatible = "mmio-sram";
118 gic: interrupt-controller@48211000 {
119 compatible = "arm,cortex-a15-gic";
120 interrupt-controller;
121 #interrupt-cells = <3>;
126 interrupt-parent = <&gic>;
129 wakeupgen: interrupt-controller@48281000 {
130 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
131 interrupt-controller;
132 #interrupt-cells = <3>;
134 interrupt-parent = <&gic>;
139 * The real OMAP interconnect network is quite complex.
145 compatible = "simple-pm-bus";
146 power-domains = <&prm_core>;
150 #address-cells = <1>;
151 #size-cells = <1>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
155 l3-noc@44000000 {
156 compatible = "ti,omap5-l3-noc";
173 target-module@48210000 {
174 compatible = "ti,sysc-omap4-simple", "ti,sysc";
175 power-domains = <&prm_mpu>;
177 clock-names = "fck";
178 #address-cells = <1>;
179 #size-cells = <1>;
183 compatible = "ti,omap4-mpu";
191 target-module@50000000 {
192 compatible = "ti,sysc-omap2", "ti,sysc";
196 reg-names = "rev", "sysc", "syss";
197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
200 ti,syss-mask = <1>;
201 ti,no-idle-on-init;
203 clock-names = "fck";
204 #address-cells = <1>;
205 #size-cells = <1>;
210 compatible = "ti,omap4430-gpmc";
212 #address-cells = <2>;
213 #size-cells = <1>;
216 dma-names = "rxtx";
217 gpmc,num-cs = <8>;
218 gpmc,num-waitpins = <4>;
219 clock-names = "fck";
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 gpio-controller;
223 #gpio-cells = <2>;
227 target-module@55082000 {
228 compatible = "ti,sysc-omap2", "ti,sysc";
232 reg-names = "rev", "sysc", "syss";
233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
236 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
240 clock-names = "fck";
242 reset-names = "rstctrl";
244 #size-cells = <1>;
245 #address-cells = <1>;
248 compatible = "ti,omap4-iommu";
251 #iommu-cells = <0>;
252 ti,iommu-bus-err-back;
257 compatible = "ti,omap5-dsp";
262 firmware-name = "omap5-dsp-fw.xe64T";
263 mboxes = <&mailbox &mbox_dsp>;
268 compatible = "ti,omap5-ipu";
270 reg-names = "l2ram";
274 firmware-name = "omap5-ipu-fw.xem4";
275 mboxes = <&mailbox &mbox_ipu>;
279 target-module@4e000000 {
280 compatible = "ti,sysc-omap2", "ti,sysc";
283 reg-names = "rev", "sysc";
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
288 #size-cells = <1>;
289 #address-cells = <1>;
292 compatible = "ti,omap5-dmm";
298 target-module@4c000000 {
299 compatible = "ti,sysc-omap4-simple", "ti,sysc";
301 reg-names = "rev";
303 clock-names = "fck";
304 ti,no-idle;
305 #address-cells = <1>;
306 #size-cells = <1>;
310 compatible = "ti,emif-4d5";
313 phy-type = <2>; /* DDR PHY type: Intelli PHY */
314 hw-caps-read-idle-ctrl;
315 hw-caps-ll-interface;
316 hw-caps-temp-alert;
320 target-module@4d000000 {
321 compatible = "ti,sysc-omap4-simple", "ti,sysc";
323 reg-names = "rev";
325 clock-names = "fck";
326 ti,no-idle;
327 #address-cells = <1>;
328 #size-cells = <1>;
332 compatible = "ti,emif-4d5";
335 phy-type = <2>; /* DDR PHY type: Intelli PHY */
336 hw-caps-read-idle-ctrl;
337 hw-caps-ll-interface;
338 hw-caps-temp-alert;
342 aes1_target: target-module@4b501000 {
343 compatible = "ti,sysc-omap2", "ti,sysc";
347 reg-names = "rev", "sysc", "syss";
348 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
350 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
354 ti,syss-mask = <1>;
357 clock-names = "fck";
358 #address-cells = <1>;
359 #size-cells = <1>;
363 compatible = "ti,omap4-aes";
367 dma-names = "tx", "rx";
371 aes2_target: target-module@4b701000 {
372 compatible = "ti,sysc-omap2", "ti,sysc";
376 reg-names = "rev", "sysc", "syss";
377 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
383 ti,syss-mask = <1>;
386 clock-names = "fck";
387 #address-cells = <1>;
388 #size-cells = <1>;
392 compatible = "ti,omap4-aes";
396 dma-names = "tx", "rx";
400 sham_target: target-module@4b100000 {
401 compatible = "ti,sysc-omap3-sham", "ti,sysc";
405 reg-names = "rev", "sysc", "syss";
406 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
408 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
411 ti,syss-mask = <1>;
414 clock-names = "fck";
415 #address-cells = <1>;
416 #size-cells = <1>;
420 compatible = "ti,omap4-sham";
424 dma-names = "rx";
434 compatible = "ti,omap5430-bandgap";
436 #thermal-sensor-cells = <1>;
439 target-module@56000000 {
440 compatible = "ti,sysc-omap4", "ti,sysc";
443 reg-names = "rev", "sysc";
444 ti,sysc-midle = <SYSC_IDLE_FORCE>,
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
451 clock-names = "fck";
452 #address-cells = <1>;
453 #size-cells = <1>;
462 target-module@58000000 {
463 compatible = "ti,sysc-omap2", "ti,sysc";
466 reg-names = "rev", "syss";
467 ti,syss-mask = <1>;
468 power-domains = <&prm_dss>;
473 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
474 #address-cells = <1>;
475 #size-cells = <1>;
479 compatible = "ti,omap5-dss";
483 clock-names = "fck";
484 #address-cells = <1>;
485 #size-cells = <1>;
488 target-module@1000 {
489 compatible = "ti,sysc-omap2", "ti,sysc";
493 reg-names = "rev", "sysc", "syss";
494 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
497 ti,sysc-midle = <SYSC_IDLE_FORCE>,
500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
504 ti,syss-mask = <1>;
506 clock-names = "fck";
507 #address-cells = <1>;
508 #size-cells = <1>;
512 compatible = "ti,omap5-dispc";
516 clock-names = "fck";
520 target-module@2000 {
521 compatible = "ti,sysc-omap2", "ti,sysc";
525 reg-names = "rev", "sysc", "syss";
526 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
529 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
531 ti,syss-mask = <1>;
533 clock-names = "fck";
534 #address-cells = <1>;
535 #size-cells = <1>;
539 compatible = "ti,omap5-rfbi";
543 clock-names = "fck", "ick";
547 target-module@4000 {
548 compatible = "ti,sysc-omap2", "ti,sysc";
552 reg-names = "rev", "sysc", "syss";
553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
556 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
560 ti,syss-mask = <1>;
561 #address-cells = <1>;
562 #size-cells = <1>;
566 compatible = "ti,omap5-dsi";
570 reg-names = "proto", "phy", "pll";
575 clock-names = "fck", "sys_clk";
577 #address-cells = <1>;
578 #size-cells = <0>;
582 target-module@9000 {
583 compatible = "ti,sysc-omap2", "ti,sysc";
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
595 ti,syss-mask = <1>;
596 #address-cells = <1>;
597 #size-cells = <1>;
601 compatible = "ti,omap5-dsi";
605 reg-names = "proto", "phy", "pll";
610 clock-names = "fck", "sys_clk";
612 #address-cells = <1>;
613 #size-cells = <0>;
617 target-module@40000 {
618 compatible = "ti,sysc-omap4", "ti,sysc";
621 reg-names = "rev", "sysc";
622 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
626 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
629 clock-names = "fck", "dss_clk";
630 #address-cells = <1>;
631 #size-cells = <1>;
635 compatible = "ti,omap5-hdmi";
640 reg-names = "wp", "pll", "phy", "core";
645 clock-names = "fck", "sys_clk";
647 dma-names = "audio_tx";
653 abb_mpu: regulator-abb-mpu {
654 compatible = "ti,abb-v2";
655 regulator-name = "abb_mpu";
656 #address-cells = <0>;
657 #size-cells = <0>;
659 ti,settling-time = <50>;
660 ti,clock-cycles = <16>;
664 reg-names = "base-address", "int-address",
665 "efuse-address", "ldo-address";
666 ti,tranxdone-status-mask = <0x80>;
668 ti,ldovbb-override-mask = <0x400>;
670 ti,ldovbb-vset-mask = <0x1F>;
683 abb_mm: regulator-abb-mm {
684 compatible = "ti,abb-v2";
685 regulator-name = "abb_mm";
686 #address-cells = <0>;
687 #size-cells = <0>;
689 ti,settling-time = <50>;
690 ti,clock-cycles = <16>;
694 reg-names = "base-address", "int-address",
695 "efuse-address", "ldo-address";
696 ti,tranxdone-status-mask = <0x80000000>;
698 ti,ldovbb-override-mask = <0x400>;
700 ti,ldovbb-vset-mask = <0x1F>;
716 polling-delay = <500>; /* milliseconds */
717 coefficients = <65 (-1791)>;
720 #include "omap5-l4.dtsi"
721 #include "omap54xx-clocks.dtsi"
724 coefficients = <117 (-2992)>;
731 #include "omap5-l4-abe.dtsi"
732 #include "omap54xx-clocks.dtsi"
736 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
738 #power-domain-cells = <0>;
742 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
744 #reset-cells = <1>;
745 #power-domain-cells = <0>;
749 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
751 #power-domain-cells = <0>;
755 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
757 #power-domain-cells = <0>;
761 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
763 #reset-cells = <1>;
764 #power-domain-cells = <0>;
768 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
770 #reset-cells = <1>;
771 #power-domain-cells = <0>;
775 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
777 #power-domain-cells = <0>;
781 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
783 #power-domain-cells = <0>;
787 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
789 #power-domain-cells = <0>;
793 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
795 #power-domain-cells = <0>;
799 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
801 #power-domain-cells = <0>;
805 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
807 #power-domain-cells = <0>;
811 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
813 #power-domain-cells = <0>;
817 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
819 #reset-cells = <1>;
823 /* Preferred always-on timer for clockevent */
825 ti,no-reset-on-init;
826 ti,no-idle;
828 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
829 assigned-clock-parents = <&sys_32k_ck>;