ti/omap/dra76x.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 		target-module@42c01900 {
13 			compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 			#address-cells = <1>;
16 			#size-cells = <1>;
20 			reg-names = "rev", "sysc", "syss";
21 			ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 			ti,syss-mask = <1>;
25 			clock-names = "fck";
30 				reg-names = "m_can", "message_ram";
31 				interrupt-parent = <&gic>;
34 				interrupt-names = "int0", "int1";
36 				clock-names = "hclk", "cclk";
37 				bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 	target-module@1b0000 {			/* 0x489b0000, ap 25 34.0 */
46 		compatible = "ti,sysc-omap4", "ti,sysc";
49 		reg-names = "rev", "sysc";
50 		ti,sysc-midle = <SYSC_IDLE_FORCE>,
52 		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
55 		clock-names = "fck";
56 		#address-cells = <1>;
57 		#size-cells = <1>;
61 			compatible = "ti,dra76-cal";
65 			reg-names = "cal_top",
69 			ti,camerrx-control = <&scm_conf 0x6dc>;
72 				#address-cells = <1>;
73 				#size-cells = <0>;
88 		#clock-cells = <0>;
89 		compatible = "ti,divider-clock";
91 		ti,max-div = <63>;
93 		ti,bit-shift = <20>;
94 		ti,latch-bit = <26>;
95 		assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
96 		assigned-clock-rates = <80000000>;
100 		#clock-cells = <0>;
101 		compatible = "ti,mux-clock";
104 		ti,bit-shift = <29>;
105 		ti,latch-bit = <26>;
106 		assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
107 		assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
111 		#clock-cells = <0>;
112 		compatible = "ti,gate-clock";
114 		ti,bit-shift = <27>;
129 	max-frequency = <96000000>;
133 	opp-1800000000 {
135 		opp-hz = /bits/ 64 <1800000000>;
136 		opp-microvolt = <1250000 950000 1250000>,
138 		opp-supported-hw = <0xFF 0x08>;
143 	ti,efuse-settings = <