Lines Matching +full:0 +full:x62000
1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00000800 0x00000800 0x000800>, /* ap 1 */
23 <0x00001000 0x00001000 0x001000>, /* ap 2 */
24 <0x00002000 0x00002000 0x002000>, /* ap 3 */
25 <0x00004000 0x00004000 0x001000>, /* ap 4 */
26 <0x00005000 0x00005000 0x001000>, /* ap 5 */
27 <0x00006000 0x00006000 0x001000>, /* ap 6 */
28 <0x00008000 0x00008000 0x002000>, /* ap 7 */
29 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
30 <0x00056000 0x00056000 0x001000>, /* ap 9 */
31 <0x00057000 0x00057000 0x001000>, /* ap 10 */
32 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
33 <0x00060000 0x00060000 0x001000>, /* ap 12 */
34 <0x00080000 0x00080000 0x008000>, /* ap 13 */
35 <0x00088000 0x00088000 0x001000>, /* ap 14 */
36 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
37 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
38 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
39 <0x000da000 0x000da000 0x001000>, /* ap 18 */
40 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
41 <0x000de000 0x000de000 0x001000>, /* ap 20 */
42 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
43 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
44 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
45 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
46 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
47 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
48 <0x00090000 0x00090000 0x008000>, /* ap 59 */
49 <0x00098000 0x00098000 0x001000>; /* ap 60 */
51 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
53 reg = <0x2000 0x4>;
57 ranges = <0x0 0x2000 0x2000>;
59 scm: scm@0 {
61 reg = <0 0x2000>;
64 ranges = <0 0 0x2000>;
66 scm_conf: scm_conf@0 {
68 reg = <0x0 0x1400>;
71 ranges = <0 0x0 0x1400>;
75 reg = <0xe00 0x4>;
86 reg = <0x554 0x4>;
92 #size-cells = <0>;
99 reg = <0x1400 0x0468>;
101 #size-cells = <0>;
106 pinctrl-single,function-mask = <0x3fffffff>;
111 reg = <0x1c04 0x0020>;
117 reg = <0x1c24 0x0024>;
122 reg = <0xb78 0xfc>;
125 ti,dma-safe-map = <0>;
131 reg = <0xc78 0x7c>;
134 ti,dma-safe-map = <0>;
140 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
142 reg = <0x5000 0x4>;
146 ranges = <0x0 0x5000 0x1000>;
148 cm_core_aon: cm_core_aon@0 {
153 reg = <0 0x2000>;
154 ranges = <0 0 0x2000>;
158 #size-cells = <0>;
166 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
168 reg = <0x8000 0x4>;
172 ranges = <0x0 0x8000 0x2000>;
174 cm_core: cm_core@0 {
178 reg = <0 0x3000>;
179 ranges = <0 0 0x3000>;
183 #size-cells = <0>;
191 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
193 reg = <0x56000 0x4>,
194 <0x5602c 0x4>,
195 <0x56028 0x4>;
211 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
215 ranges = <0x0 0x56000 0x1000>;
217 sdma: dma-controller@0 {
219 reg = <0x0 0x1000>;
230 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
235 ranges = <0x0 0x5e000 0x2000>;
238 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
240 reg = <0x80000 0x4>,
241 <0x80010 0x4>,
242 <0x80014 0x4>;
251 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
255 ranges = <0x0 0x80000 0x8000>;
257 ocp2scp@0 {
261 ranges = <0 0 0x8000>;
262 reg = <0x0 0x20>;
266 reg = <0x4000 0x400>;
267 syscon-phy-power = <&scm_conf 0x300>;
272 #phy-cells = <0>;
278 reg = <0x5000 0x400>;
279 syscon-phy-power = <&scm_conf 0xe74>;
284 #phy-cells = <0>;
289 reg = <0x4400 0x80>,
290 <0x4800 0x64>,
291 <0x4c00 0x40>;
293 syscon-phy-power = <&scm_conf 0x370>;
300 #phy-cells = <0>;
305 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
307 reg = <0x90000 0x4>,
308 <0x90010 0x4>,
309 <0x90014 0x4>;
318 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
322 ranges = <0x0 0x90000 0x8000>;
324 ocp2scp@0 {
328 ranges = <0 0 0x8000>;
329 reg = <0x0 0x20>;
333 reg = <0x4000 0x80>, /* phy_rx */
334 <0x4400 0x64>; /* phy_tx */
336 syscon-phy-power = <&scm_conf_pcie 0x1c>;
337 syscon-pcs = <&scm_conf_pcie 0x10>;
348 #phy-cells = <0>;
353 reg = <0x5000 0x80>, /* phy_rx */
354 <0x5400 0x64>; /* phy_tx */
356 syscon-phy-power = <&scm_conf_pcie 0x20>;
357 syscon-pcs = <&scm_conf_pcie 0x10>;
368 #phy-cells = <0>;
374 reg = <0x6000 0x80>, /* phy_rx */
375 <0x6400 0x64>, /* phy_tx */
376 <0x6800 0x40>; /* pll_ctrl */
378 syscon-phy-power = <&scm_conf 0x374>;
382 syscon-pllreset = <&scm_conf 0x3fc>;
383 #phy-cells = <0>;
388 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
393 ranges = <0x0 0xa0000 0x8000>;
396 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
398 reg = <0xd9038 0x4>;
406 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
410 ranges = <0x0 0xd9000 0x1000>;
415 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
417 reg = <0xdd038 0x4>;
425 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
429 ranges = <0x0 0xdd000 0x1000>;
434 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
439 ranges = <0x0 0xe0000 0x1000>;
442 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
444 reg = <0xf4000 0x4>,
445 <0xf4010 0x4>;
452 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
456 ranges = <0x0 0xf4000 0x1000>;
458 mailbox1: mailbox@0 {
460 reg = <0x0 0x200>;
471 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
473 reg = <0xf6000 0x4>,
474 <0xf6010 0x4>,
475 <0xf6014 0x4>;
485 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
489 ranges = <0x0 0xf6000 0x1000>;
491 hwspinlock: spinlock@0 {
493 reg = <0x0 0x1000>;
499 segment@100000 { /* 0x4a100000 */
503 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
504 <0x00003000 0x00103000 0x001000>, /* ap 28 */
505 <0x00008000 0x00108000 0x001000>, /* ap 29 */
506 <0x00009000 0x00109000 0x001000>, /* ap 30 */
507 <0x00040000 0x00140000 0x010000>, /* ap 31 */
508 <0x00050000 0x00150000 0x001000>, /* ap 32 */
509 <0x00051000 0x00151000 0x001000>, /* ap 33 */
510 <0x00052000 0x00152000 0x001000>, /* ap 34 */
511 <0x00053000 0x00153000 0x001000>, /* ap 35 */
512 <0x00054000 0x00154000 0x001000>, /* ap 36 */
513 <0x00055000 0x00155000 0x001000>, /* ap 37 */
514 <0x00056000 0x00156000 0x001000>, /* ap 38 */
515 <0x00057000 0x00157000 0x001000>, /* ap 39 */
516 <0x00058000 0x00158000 0x001000>, /* ap 40 */
517 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
518 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
519 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
520 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
521 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
522 <0x00060000 0x00160000 0x001000>, /* ap 48 */
523 <0x00061000 0x00161000 0x001000>, /* ap 49 */
524 <0x00062000 0x00162000 0x001000>, /* ap 50 */
525 <0x00063000 0x00163000 0x001000>, /* ap 51 */
526 <0x00064000 0x00164000 0x001000>, /* ap 52 */
527 <0x00065000 0x00165000 0x001000>, /* ap 53 */
528 <0x00066000 0x00166000 0x001000>, /* ap 54 */
529 <0x00067000 0x00167000 0x001000>, /* ap 55 */
530 <0x00068000 0x00168000 0x001000>, /* ap 56 */
531 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
532 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
533 <0x00071000 0x00171000 0x001000>, /* ap 61 */
534 <0x00072000 0x00172000 0x001000>, /* ap 62 */
535 <0x00073000 0x00173000 0x001000>, /* ap 63 */
536 <0x00074000 0x00174000 0x001000>, /* ap 64 */
537 <0x00075000 0x00175000 0x001000>, /* ap 65 */
538 <0x00076000 0x00176000 0x001000>, /* ap 66 */
539 <0x00077000 0x00177000 0x001000>, /* ap 67 */
540 <0x00078000 0x00178000 0x001000>, /* ap 68 */
541 <0x00081000 0x00181000 0x001000>, /* ap 69 */
542 <0x00082000 0x00182000 0x001000>, /* ap 70 */
543 <0x00083000 0x00183000 0x001000>, /* ap 71 */
544 <0x00084000 0x00184000 0x001000>, /* ap 72 */
545 <0x00085000 0x00185000 0x001000>, /* ap 73 */
546 <0x00086000 0x00186000 0x001000>, /* ap 74 */
547 <0x00087000 0x00187000 0x001000>, /* ap 75 */
548 <0x00088000 0x00188000 0x001000>, /* ap 76 */
549 <0x00069000 0x00169000 0x001000>, /* ap 103 */
550 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
551 <0x00079000 0x00179000 0x001000>, /* ap 105 */
552 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
553 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
554 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
555 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
556 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
557 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
558 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
559 <0x00059000 0x00159000 0x001000>, /* ap 125 */
560 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
563 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
568 ranges = <0x0 0x2000 0x1000>;
571 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
576 ranges = <0x0 0x8000 0x1000>;
579 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
581 reg = <0x400fc 4>,
582 <0x41100 4>;
592 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
596 ranges = <0x0 0x40000 0x10000>;
598 sata: sata@0 {
600 reg = <0 0x1100>, <0x1100 0x8>;
605 ports-implemented = <0x1>;
609 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
614 ranges = <0x0 0x51000 0x1000>;
617 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
622 ranges = <0x0 0x53000 0x1000>;
625 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
630 ranges = <0x0 0x55000 0x1000>;
633 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
638 ranges = <0x0 0x57000 0x1000>;
641 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
646 ranges = <0x0 0x59000 0x1000>;
649 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
654 ranges = <0x0 0x5b000 0x1000>;
657 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
662 ranges = <0x0 0x5d000 0x1000>;
665 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
670 ranges = <0x0 0x5f000 0x1000>;
673 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
678 ranges = <0x0 0x61000 0x1000>;
681 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
686 ranges = <0x0 0x63000 0x1000>;
689 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
694 ranges = <0x0 0x65000 0x1000>;
697 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
702 ranges = <0x0 0x67000 0x1000>;
705 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
710 ranges = <0x0 0x69000 0x1000>;
713 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
718 ranges = <0x0 0x6b000 0x1000>;
721 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
726 ranges = <0x0 0x6d000 0x1000>;
729 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
734 ranges = <0x0 0x71000 0x1000>;
737 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
742 ranges = <0x0 0x73000 0x1000>;
745 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
750 ranges = <0x0 0x75000 0x1000>;
753 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
758 ranges = <0x0 0x77000 0x1000>;
761 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
766 ranges = <0x0 0x79000 0x1000>;
769 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
774 ranges = <0x0 0x7b000 0x1000>;
777 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
782 ranges = <0x0 0x7d000 0x1000>;
785 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
790 ranges = <0x0 0x81000 0x1000>;
793 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
798 ranges = <0x0 0x83000 0x1000>;
801 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
806 ranges = <0x0 0x85000 0x1000>;
809 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
814 ranges = <0x0 0x87000 0x1000>;
818 segment@200000 { /* 0x4a200000 */
822 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
823 <0x00019000 0x00219000 0x001000>, /* ap 44 */
824 <0x00000000 0x00200000 0x001000>, /* ap 77 */
825 <0x00001000 0x00201000 0x001000>, /* ap 78 */
826 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
827 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
828 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
829 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
830 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
831 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
832 <0x00010000 0x00210000 0x001000>, /* ap 85 */
833 <0x00011000 0x00211000 0x001000>, /* ap 86 */
834 <0x00012000 0x00212000 0x001000>, /* ap 87 */
835 <0x00013000 0x00213000 0x001000>, /* ap 88 */
836 <0x00014000 0x00214000 0x001000>, /* ap 89 */
837 <0x00015000 0x00215000 0x001000>, /* ap 90 */
838 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
839 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
840 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
841 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
842 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
843 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
844 <0x00020000 0x00220000 0x001000>, /* ap 97 */
845 <0x00021000 0x00221000 0x001000>, /* ap 98 */
846 <0x00024000 0x00224000 0x001000>, /* ap 99 */
847 <0x00025000 0x00225000 0x001000>, /* ap 100 */
848 <0x00026000 0x00226000 0x001000>, /* ap 101 */
849 <0x00027000 0x00227000 0x001000>, /* ap 102 */
850 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
851 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
852 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
853 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
854 <0x00030000 0x00230000 0x001000>, /* ap 113 */
855 <0x00031000 0x00231000 0x001000>, /* ap 114 */
856 <0x00032000 0x00232000 0x001000>, /* ap 115 */
857 <0x00033000 0x00233000 0x001000>, /* ap 116 */
858 <0x00034000 0x00234000 0x001000>, /* ap 117 */
859 <0x00035000 0x00235000 0x001000>, /* ap 118 */
860 <0x00036000 0x00236000 0x001000>, /* ap 119 */
861 <0x00037000 0x00237000 0x001000>, /* ap 120 */
862 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
863 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
865 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
870 ranges = <0x0 0x0 0x1000>;
873 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
878 ranges = <0x0 0xa000 0x1000>;
881 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
886 ranges = <0x0 0xc000 0x1000>;
889 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
894 ranges = <0x0 0xe000 0x1000>;
897 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
902 ranges = <0x0 0x10000 0x1000>;
905 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
910 ranges = <0x0 0x12000 0x1000>;
913 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
918 ranges = <0x0 0x14000 0x1000>;
921 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
926 ranges = <0x0 0x18000 0x1000>;
929 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
934 ranges = <0x0 0x1a000 0x1000>;
937 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
942 ranges = <0x0 0x1c000 0x1000>;
945 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
950 ranges = <0x0 0x1e000 0x1000>;
953 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
958 ranges = <0x0 0x20000 0x1000>;
961 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
966 ranges = <0x0 0x24000 0x1000>;
969 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
974 ranges = <0x0 0x26000 0x1000>;
977 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
982 ranges = <0x0 0x2a000 0x1000>;
985 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
990 ranges = <0x0 0x2c000 0x1000>;
993 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
998 ranges = <0x0 0x2e000 0x1000>;
1001 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
1006 ranges = <0x0 0x30000 0x1000>;
1009 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
1014 ranges = <0x0 0x32000 0x1000>;
1017 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
1022 ranges = <0x0 0x34000 0x1000>;
1025 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1030 ranges = <0x0 0x36000 0x1000>;
1035 &l4_per1 { /* 0x48000000 */
1038 clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
1040 reg = <0x48000000 0x800>,
1041 <0x48000800 0x800>,
1042 <0x48001000 0x400>,
1043 <0x48001400 0x400>,
1044 <0x48001800 0x400>,
1045 <0x48001c00 0x400>;
1049 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1050 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1052 segment@0 { /* 0x48000000 */
1056 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1057 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1058 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1059 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1060 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1061 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1062 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1063 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1064 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1065 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1066 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1067 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1068 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1069 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1070 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1071 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1072 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1073 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1074 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1075 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1076 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1077 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1078 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1079 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1080 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1081 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1082 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1083 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1084 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1085 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1086 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1087 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1088 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1089 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1090 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1091 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1092 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1093 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1094 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1095 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1096 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1097 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1098 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1099 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1100 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1101 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1102 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1103 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1104 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1105 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1106 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1107 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1108 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1109 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1110 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1111 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1112 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1113 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1114 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1115 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1116 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1117 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1118 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1119 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1120 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1121 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1122 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1123 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1124 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1125 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1126 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1127 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1128 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1129 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1130 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1131 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1132 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1133 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1134 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1135 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1136 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1137 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1138 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1139 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1140 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1142 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1144 reg = <0x20050 0x4>,
1145 <0x20054 0x4>,
1146 <0x20058 0x4>;
1157 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1161 ranges = <0x0 0x20000 0x1000>;
1163 uart3: serial@0 {
1165 reg = <0x0 0x100>;
1174 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1176 reg = <0x32000 0x4>,
1177 <0x32010 0x4>;
1186 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1190 ranges = <0x0 0x32000 0x1000>;
1192 timer2: timer@0 {
1194 reg = <0x0 0x80>;
1201 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
1203 reg = <0x34000 0x4>,
1204 <0x34010 0x4>;
1213 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1217 ranges = <0x0 0x34000 0x1000>;
1219 timer3: timer@0 {
1221 reg = <0x0 0x80>;
1228 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1230 reg = <0x36000 0x4>,
1231 <0x36010 0x4>;
1240 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1244 ranges = <0x0 0x36000 0x1000>;
1246 timer4: timer@0 {
1248 reg = <0x0 0x80>;
1255 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1257 reg = <0x3e000 0x4>,
1258 <0x3e010 0x4>;
1267 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1271 ranges = <0x0 0x3e000 0x1000>;
1273 timer9: timer@0 {
1275 reg = <0x0 0x80>;
1282 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1284 reg = <0x51000 0x4>,
1285 <0x51010 0x4>,
1286 <0x51114 0x4>;
1297 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1302 ranges = <0x0 0x51000 0x1000>;
1304 gpio7: gpio@0 {
1306 reg = <0x0 0x200>;
1315 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1317 reg = <0x53000 0x4>,
1318 <0x53010 0x4>,
1319 <0x53114 0x4>;
1330 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1335 ranges = <0x0 0x53000 0x1000>;
1337 gpio8: gpio@0 {
1339 reg = <0x0 0x200>;
1348 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1350 reg = <0x55000 0x4>,
1351 <0x55010 0x4>,
1352 <0x55114 0x4>;
1363 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1368 ranges = <0x0 0x55000 0x1000>;
1370 gpio2: gpio@0 {
1372 reg = <0x0 0x200>;
1381 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
1383 reg = <0x57000 0x4>,
1384 <0x57010 0x4>,
1385 <0x57114 0x4>;
1396 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1401 ranges = <0x0 0x57000 0x1000>;
1403 gpio3: gpio@0 {
1405 reg = <0x0 0x200>;
1414 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1416 reg = <0x59000 0x4>,
1417 <0x59010 0x4>,
1418 <0x59114 0x4>;
1429 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1434 ranges = <0x0 0x59000 0x1000>;
1436 gpio4: gpio@0 {
1438 reg = <0x0 0x200>;
1447 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1449 reg = <0x5b000 0x4>,
1450 <0x5b010 0x4>,
1451 <0x5b114 0x4>;
1462 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1467 ranges = <0x0 0x5b000 0x1000>;
1469 gpio5: gpio@0 {
1471 reg = <0x0 0x200>;
1480 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1482 reg = <0x5d000 0x4>,
1483 <0x5d010 0x4>,
1484 <0x5d114 0x4>;
1495 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1500 ranges = <0x0 0x5d000 0x1000>;
1502 gpio6: gpio@0 {
1504 reg = <0x0 0x200>;
1513 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1515 reg = <0x60000 0x8>,
1516 <0x60010 0x8>,
1517 <0x60090 0x8>;
1529 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1533 ranges = <0x0 0x60000 0x1000>;
1535 i2c3: i2c@0 {
1537 reg = <0x0 0x100>;
1540 #size-cells = <0>;
1545 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1547 reg = <0x66050 0x4>,
1548 <0x66054 0x4>,
1549 <0x66058 0x4>;
1560 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1564 ranges = <0x0 0x66000 0x1000>;
1566 uart5: serial@0 {
1568 reg = <0x0 0x100>;
1577 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1579 reg = <0x68050 0x4>,
1580 <0x68054 0x4>,
1581 <0x68058 0x4>;
1592 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1596 ranges = <0x0 0x68000 0x1000>;
1598 uart6: serial@0 {
1600 reg = <0x0 0x100>;
1609 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1611 reg = <0x6a050 0x4>,
1612 <0x6a054 0x4>,
1613 <0x6a058 0x4>;
1624 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1628 ranges = <0x0 0x6a000 0x1000>;
1630 uart1: serial@0 {
1632 reg = <0x0 0x100>;
1641 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1643 reg = <0x6c050 0x4>,
1644 <0x6c054 0x4>,
1645 <0x6c058 0x4>;
1656 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1660 ranges = <0x0 0x6c000 0x1000>;
1662 uart2: serial@0 {
1664 reg = <0x0 0x100>;
1673 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1675 reg = <0x6e050 0x4>,
1676 <0x6e054 0x4>,
1677 <0x6e058 0x4>;
1688 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1692 ranges = <0x0 0x6e000 0x1000>;
1694 uart4: serial@0 {
1696 reg = <0x0 0x100>;
1705 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1707 reg = <0x70000 0x8>,
1708 <0x70010 0x8>,
1709 <0x70090 0x8>;
1721 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1725 ranges = <0x0 0x70000 0x1000>;
1727 i2c1: i2c@0 {
1729 reg = <0x0 0x100>;
1732 #size-cells = <0>;
1737 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1739 reg = <0x72000 0x8>,
1740 <0x72010 0x8>,
1741 <0x72090 0x8>;
1753 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1757 ranges = <0x0 0x72000 0x1000>;
1759 i2c2: i2c@0 {
1761 reg = <0x0 0x100>;
1764 #size-cells = <0>;
1769 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1771 reg = <0x78000 0x4>,
1772 <0x78010 0x4>,
1773 <0x78014 0x4>;
1784 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1788 ranges = <0x0 0x78000 0x1000>;
1790 elm: elm@0 {
1792 reg = <0x0 0xfc0>; /* device IO registers */
1798 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1800 reg = <0x7a000 0x8>,
1801 <0x7a010 0x8>,
1802 <0x7a090 0x8>;
1814 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1818 ranges = <0x0 0x7a000 0x1000>;
1820 i2c4: i2c@0 {
1822 reg = <0x0 0x100>;
1825 #size-cells = <0>;
1830 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1832 reg = <0x7c000 0x8>,
1833 <0x7c010 0x8>,
1834 <0x7c090 0x8>;
1846 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1850 ranges = <0x0 0x7c000 0x1000>;
1852 i2c5: i2c@0 {
1854 reg = <0x0 0x100>;
1857 #size-cells = <0>;
1862 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1864 reg = <0x86000 0x4>,
1865 <0x86010 0x4>;
1874 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1878 ranges = <0x0 0x86000 0x1000>;
1880 timer10: timer@0 {
1882 reg = <0x0 0x80>;
1889 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1891 reg = <0x88000 0x4>,
1892 <0x88010 0x4>;
1901 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1905 ranges = <0x0 0x88000 0x1000>;
1907 timer11: timer@0 {
1909 reg = <0x0 0x80>;
1916 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1918 reg = <0x91fe0 0x4>,
1919 <0x91fe4 0x4>;
1925 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1929 ranges = <0x0 0x90000 0x2000>;
1931 rng: rng@0 {
1933 reg = <0x0 0x2000>;
1940 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1942 reg = <0x98000 0x4>,
1943 <0x98010 0x4>;
1952 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1956 ranges = <0x0 0x98000 0x1000>;
1958 mcspi1: spi@0 {
1960 reg = <0x0 0x200>;
1963 #size-cells = <0>;
1979 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1981 reg = <0x9a000 0x4>,
1982 <0x9a010 0x4>;
1991 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1995 ranges = <0x0 0x9a000 0x1000>;
1997 mcspi2: spi@0 {
1999 reg = <0x0 0x200>;
2002 #size-cells = <0>;
2013 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
2015 reg = <0x9c000 0x4>,
2016 <0x9c010 0x4>;
2029 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2033 ranges = <0x0 0x9c000 0x1000>;
2035 mmc1: mmc@0 {
2037 reg = <0x0 0x400>;
2047 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2052 ranges = <0x0 0xa2000 0x1000>;
2055 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2060 ranges = <0x00000000 0x000a4000 0x00001000>,
2061 <0x00001000 0x000a5000 0x00001000>;
2064 des_target: target-module@a5000 { /* 0x480a5000 */
2066 reg = <0xa5030 0x4>,
2067 <0xa5034 0x4>,
2068 <0xa5038 0x4>;
2078 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2082 ranges = <0 0xa5000 0x00001000>;
2084 des: des@0 {
2086 reg = <0 0xa0>;
2095 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2100 ranges = <0x0 0xa8000 0x4000>;
2103 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2105 reg = <0xad000 0x4>,
2106 <0xad010 0x4>;
2119 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2123 ranges = <0x0 0xad000 0x1000>;
2125 mmc3: mmc@0 {
2127 reg = <0x0 0x400>;
2133 sdhci-caps-mask = <0x0 0x400000>;
2137 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2139 reg = <0xb2000 0x4>,
2140 <0xb2014 0x4>,
2141 <0xb2018 0x4>;
2148 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2152 ranges = <0x0 0xb2000 0x1000>;
2154 hdqw1w: 1w@0 {
2156 reg = <0x0 0x1000>;
2161 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2163 reg = <0xb4000 0x4>,
2164 <0xb4010 0x4>;
2177 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2181 ranges = <0x0 0xb4000 0x1000>;
2183 mmc2: mmc@0 {
2185 reg = <0x0 0x400>;
2190 sdhci-caps-mask = <0x7 0x0>;
2197 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2199 reg = <0xb8000 0x4>,
2200 <0xb8010 0x4>;
2209 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2213 ranges = <0x0 0xb8000 0x1000>;
2215 mcspi3: spi@0 {
2217 reg = <0x0 0x200>;
2220 #size-cells = <0>;
2228 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2230 reg = <0xba000 0x4>,
2231 <0xba010 0x4>;
2240 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2244 ranges = <0x0 0xba000 0x1000>;
2246 mcspi4: spi@0 {
2248 reg = <0x0 0x200>;
2251 #size-cells = <0>;
2259 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2261 reg = <0xd1000 0x4>,
2262 <0xd1010 0x4>;
2275 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2279 ranges = <0x0 0xd1000 0x1000>;
2281 mmc4: mmc@0 {
2283 reg = <0x0 0x400>;
2288 sdhci-caps-mask = <0x0 0x400000>;
2292 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2297 ranges = <0x0 0xd5000 0x1000>;
2301 segment@200000 { /* 0x48200000 */
2308 &l4_per2 { /* 0x48400000 */
2311 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2313 reg = <0x48400000 0x800>,
2314 <0x48400800 0x800>,
2315 <0x48401000 0x400>,
2316 <0x48401400 0x400>,
2317 <0x48401800 0x400>;
2321 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2322 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2323 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2324 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2325 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2326 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2327 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2328 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2329 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2331 segment@0 { /* 0x48400000 */
2335 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2336 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2337 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2338 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2339 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2340 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2341 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2342 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2343 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2344 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2345 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2346 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2347 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2348 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2349 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2350 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2351 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2352 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2353 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2354 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2355 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2356 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2357 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2358 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2359 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2360 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2361 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2362 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2363 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2364 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2365 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2366 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2367 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2368 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2369 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2370 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2371 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2372 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2373 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2374 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2375 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2376 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2377 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2378 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2379 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2380 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2381 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2382 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2383 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2384 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2385 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2386 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2387 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2388 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2389 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2390 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2391 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2392 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2393 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2394 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2395 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2396 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2397 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2398 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2399 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2400 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2401 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2402 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2403 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2404 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2405 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2407 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2409 reg = <0x20050 0x4>,
2410 <0x20054 0x4>,
2411 <0x20058 0x4>;
2422 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2426 ranges = <0x0 0x20000 0x1000>;
2428 uart7: serial@0 {
2430 reg = <0x0 0x100>;
2437 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2439 reg = <0x22050 0x4>,
2440 <0x22054 0x4>,
2441 <0x22058 0x4>;
2452 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2456 ranges = <0x0 0x22000 0x1000>;
2458 uart8: serial@0 {
2460 reg = <0x0 0x100>;
2467 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2469 reg = <0x24050 0x4>,
2470 <0x24054 0x4>,
2471 <0x24058 0x4>;
2482 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2486 ranges = <0x0 0x24000 0x1000>;
2488 uart9: serial@0 {
2490 reg = <0x0 0x100>;
2497 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2502 ranges = <0x0 0x2c000 0x1000>;
2505 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2510 ranges = <0x0 0x36000 0x1000>;
2513 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2518 ranges = <0x0 0x3a000 0x1000>;
2521 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2523 reg = <0x3c000 0x4>;
2525 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2529 ranges = <0x0 0x3c000 0x1000>;
2531 atl: atl@0 {
2533 reg = <0x0 0x3ff>;
2542 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2544 reg = <0x3e000 0x4>,
2545 <0x3e004 0x4>;
2552 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2556 ranges = <0x0 0x3e000 0x1000>;
2558 epwmss0: epwmss@0 {
2560 reg = <0x0 0x30>;
2564 ranges = <0 0 0x1000>;
2570 reg = <0x100 0x80>;
2580 reg = <0x200 0x80>;
2588 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2590 reg = <0x40000 0x4>,
2591 <0x40004 0x4>;
2598 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2602 ranges = <0x0 0x40000 0x1000>;
2604 epwmss1: epwmss@0 {
2606 reg = <0x0 0x30>;
2610 ranges = <0 0 0x1000>;
2616 reg = <0x100 0x80>;
2626 reg = <0x200 0x80>;
2634 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2636 reg = <0x42000 0x4>,
2637 <0x42004 0x4>;
2644 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2648 ranges = <0x0 0x42000 0x1000>;
2650 epwmss2: epwmss@0 {
2652 reg = <0x0 0x30>;
2656 ranges = <0 0 0x1000>;
2662 reg = <0x100 0x80>;
2672 reg = <0x200 0x80>;
2680 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2685 ranges = <0x0 0x46000 0x1000>;
2688 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2693 ranges = <0x0 0x48000 0x1000>;
2696 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2701 ranges = <0x0 0x4a000 0x1000>;
2704 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2709 ranges = <0x0 0x4c000 0x1000>;
2712 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2717 ranges = <0x0 0x50000 0x1000>;
2720 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2725 ranges = <0x0 0x54000 0x1000>;
2728 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2733 ranges = <0x0 0x58000 0x2000>;
2736 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2741 ranges = <0x0 0x5b000 0x1000>;
2744 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2749 ranges = <0x0 0x5d000 0x1000>;
2752 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2754 reg = <0x60000 0x4>,
2755 <0x60004 0x4>;
2761 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2767 ranges = <0x0 0x60000 0x2000>,
2768 <0x45800000 0x45800000 0x400000>;
2770 mcasp1: mcasp@0 {
2772 reg = <0x0 0x2000>,
2773 <0x45800000 0x1000>; /* L3 data port */
2780 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2788 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2790 reg = <0x64000 0x4>,
2791 <0x64004 0x4>;
2797 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2803 ranges = <0x0 0x64000 0x2000>,
2804 <0x45c00000 0x45c00000 0x400000>;
2806 mcasp2: mcasp@0 {
2808 reg = <0x0 0x2000>,
2809 <0x45c00000 0x1000>; /* L3 data port */
2816 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2824 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2826 reg = <0x68000 0x4>,
2827 <0x68004 0x4>;
2833 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2838 ranges = <0x0 0x68000 0x2000>,
2839 <0x46000000 0x46000000 0x400000>;
2841 mcasp3: mcasp@0 {
2843 reg = <0x0 0x2000>,
2844 <0x46000000 0x1000>; /* L3 data port */
2851 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2858 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2860 reg = <0x6c000 0x4>,
2861 <0x6c004 0x4>;
2867 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2872 ranges = <0x0 0x6c000 0x2000>,
2873 <0x48436000 0x48436000 0x400000>;
2875 mcasp4: mcasp@0 {
2877 reg = <0x0 0x2000>,
2878 <0x48436000 0x1000>; /* L3 data port */
2885 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2892 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2894 reg = <0x70000 0x4>,
2895 <0x70004 0x4>;
2901 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2906 ranges = <0x0 0x70000 0x2000>,
2907 <0x4843a000 0x4843a000 0x400000>;
2909 mcasp5: mcasp@0 {
2911 reg = <0x0 0x2000>,
2912 <0x4843a000 0x1000>; /* L3 data port */
2919 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2926 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2928 reg = <0x74000 0x4>,
2929 <0x74004 0x4>;
2935 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2940 ranges = <0x0 0x74000 0x2000>,
2941 <0x4844c000 0x4844c000 0x400000>;
2943 mcasp6: mcasp@0 {
2945 reg = <0x0 0x2000>,
2946 <0x4844c000 0x1000>; /* L3 data port */
2953 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2960 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2962 reg = <0x78000 0x4>,
2963 <0x78004 0x4>;
2969 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2974 ranges = <0x0 0x78000 0x2000>,
2975 <0x48450000 0x48450000 0x400000>;
2977 mcasp7: mcasp@0 {
2979 reg = <0x0 0x2000>,
2980 <0x48450000 0x1000>; /* L3 data port */
2987 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2994 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2996 reg = <0x7c000 0x4>,
2997 <0x7c004 0x4>;
3003 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3008 ranges = <0x0 0x7c000 0x2000>,
3009 <0x48454000 0x48454000 0x400000>;
3011 mcasp8: mcasp@0 {
3013 reg = <0x0 0x2000>,
3014 <0x48454000 0x1000>; /* L3 data port */
3021 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3028 target-module@80000 { /* 0x48480000, ap 31 16.0 */
3030 reg = <0x80020 0x4>;
3032 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3036 ranges = <0x0 0x80000 0x2000>;
3038 dcan2: can@0 {
3040 reg = <0x0 0x2000>;
3041 syscon-raminit = <&scm_conf 0x558 1>;
3048 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3050 reg = <0x85200 0x4>,
3051 <0x85208 0x4>,
3052 <0x85204 0x4>;
3054 ti,sysc-mask = <0>;
3060 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3064 ranges = <0x0 0x84000 0x4000>;
3074 mac_sw: switch@0 {
3076 reg = <0x0 0x4000>;
3077 ranges = <0 0 0x4000>;
3093 #size-cells = <0>;
3115 #size-cells = <0>;
3117 reg = <0x1000 0x100>;
3129 &l4_per3 { /* 0x48800000 */
3132 clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
3134 reg = <0x48800000 0x800>,
3135 <0x48800800 0x800>,
3136 <0x48801000 0x400>,
3137 <0x48801400 0x400>,
3138 <0x48801800 0x400>;
3142 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3144 segment@0 { /* 0x48800000 */
3148 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3149 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3150 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3151 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3152 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3153 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3154 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3155 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3156 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3157 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3158 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3159 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3160 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3161 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3162 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3163 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3164 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3165 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3166 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3167 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3168 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3169 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3170 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3171 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3172 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3173 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3174 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3175 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3176 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3177 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3178 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3179 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3180 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3181 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3182 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3183 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3184 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3185 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3186 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3187 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3188 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3189 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3190 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3191 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3192 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3193 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3194 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3195 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3196 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3197 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3198 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3199 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3200 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3201 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3202 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3203 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3204 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3205 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3206 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3207 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3208 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3209 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3210 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3211 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3212 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3213 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3214 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3215 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3216 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3217 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3218 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3219 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3220 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3221 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3222 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3223 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3224 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3225 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3226 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3227 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3228 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3229 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3230 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3231 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3232 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3233 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3234 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3235 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3236 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3237 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3238 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3239 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3240 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3241 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3242 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3243 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3244 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3246 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3248 reg = <0x2000 0x4>,
3249 <0x2010 0x4>;
3256 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3260 ranges = <0x0 0x2000 0x1000>;
3262 mailbox13: mailbox@0 {
3264 reg = <0x0 0x200>;
3276 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3281 ranges = <0x0 0x4000 0x1000>;
3284 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3289 ranges = <0x0 0xa000 0x1000>;
3292 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3297 ranges = <0x0 0x10000 0x1000>;
3300 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3305 ranges = <0x0 0x16000 0x1000>;
3308 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3313 ranges = <0x0 0x1c000 0x1000>;
3316 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3321 ranges = <0x0 0x1e000 0x1000>;
3324 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3326 reg = <0x20000 0x4>,
3327 <0x20010 0x4>;
3336 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3340 ranges = <0x0 0x20000 0x1000>;
3342 timer5: timer@0 {
3344 reg = <0x0 0x80>;
3351 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3353 reg = <0x22000 0x4>,
3354 <0x22010 0x4>;
3363 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3367 ranges = <0x0 0x22000 0x1000>;
3369 timer6: timer@0 {
3371 reg = <0x0 0x80>;
3378 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3380 reg = <0x24000 0x4>,
3381 <0x24010 0x4>;
3390 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3394 ranges = <0x0 0x24000 0x1000>;
3396 timer7: timer@0 {
3398 reg = <0x0 0x80>;
3405 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3407 reg = <0x26000 0x4>,
3408 <0x26010 0x4>;
3417 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3421 ranges = <0x0 0x26000 0x1000>;
3423 timer8: timer@0 {
3425 reg = <0x0 0x80>;
3432 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3434 reg = <0x28000 0x4>,
3435 <0x28010 0x4>;
3444 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3448 ranges = <0x0 0x28000 0x1000>;
3450 timer13: timer@0 {
3452 reg = <0x0 0x80>;
3460 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3462 reg = <0x2a000 0x4>,
3463 <0x2a010 0x4>;
3472 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3476 ranges = <0x0 0x2a000 0x1000>;
3478 timer14: timer@0 {
3480 reg = <0x0 0x80>;
3487 timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3489 reg = <0x2c000 0x4>,
3490 <0x2c010 0x4>;
3499 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3503 ranges = <0x0 0x2c000 0x1000>;
3505 timer15: timer@0 {
3507 reg = <0x0 0x80>;
3515 timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3517 reg = <0x2e000 0x4>,
3518 <0x2e010 0x4>;
3527 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3531 ranges = <0x0 0x2e000 0x1000>;
3533 timer16: timer@0 {
3535 reg = <0x0 0x80>;
3543 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3545 reg = <0x38074 0x4>,
3546 <0x38078 0x4>;
3553 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3557 ranges = <0x0 0x38000 0x1000>;
3559 rtc: rtc@0 {
3561 reg = <0x0 0x100>;
3568 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3570 reg = <0x3a000 0x4>,
3571 <0x3a010 0x4>;
3578 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3582 ranges = <0x0 0x3a000 0x1000>;
3584 mailbox2: mailbox@0 {
3586 reg = <0x0 0x200>;
3598 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3600 reg = <0x3c000 0x4>,
3601 <0x3c010 0x4>;
3608 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3612 ranges = <0x0 0x3c000 0x1000>;
3614 mailbox3: mailbox@0 {
3616 reg = <0x0 0x200>;
3628 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3630 reg = <0x3e000 0x4>,
3631 <0x3e010 0x4>;
3638 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3642 ranges = <0x0 0x3e000 0x1000>;
3644 mailbox4: mailbox@0 {
3646 reg = <0x0 0x200>;
3658 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3660 reg = <0x40000 0x4>,
3661 <0x40010 0x4>;
3668 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3672 ranges = <0x0 0x40000 0x1000>;
3674 mailbox5: mailbox@0 {
3676 reg = <0x0 0x200>;
3688 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3690 reg = <0x42000 0x4>,
3691 <0x42010 0x4>;
3698 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3702 ranges = <0x0 0x42000 0x1000>;
3704 mailbox6: mailbox@0 {
3706 reg = <0x0 0x200>;
3718 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3720 reg = <0x44000 0x4>,
3721 <0x44010 0x4>;
3728 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3732 ranges = <0x0 0x44000 0x1000>;
3734 mailbox7: mailbox@0 {
3736 reg = <0x0 0x200>;
3748 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3750 reg = <0x46000 0x4>,
3751 <0x46010 0x4>;
3758 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3762 ranges = <0x0 0x46000 0x1000>;
3764 mailbox8: mailbox@0 {
3766 reg = <0x0 0x200>;
3778 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3783 ranges = <0x0 0x48000 0x1000>;
3786 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3791 ranges = <0x0 0x4a000 0x1000>;
3794 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3799 ranges = <0x0 0x4c000 0x1000>;
3802 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3807 ranges = <0x0 0x4e000 0x1000>;
3810 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3815 ranges = <0x0 0x50000 0x1000>;
3818 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3823 ranges = <0x0 0x52000 0x1000>;
3826 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3831 ranges = <0x0 0x54000 0x1000>;
3834 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3839 ranges = <0x0 0x56000 0x1000>;
3842 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3847 ranges = <0x0 0x58000 0x1000>;
3850 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3855 ranges = <0x0 0x5a000 0x1000>;
3858 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3863 ranges = <0x0 0x5c000 0x1000>;
3866 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3868 reg = <0x5e000 0x4>,
3869 <0x5e010 0x4>;
3876 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3880 ranges = <0x0 0x5e000 0x1000>;
3882 mailbox9: mailbox@0 {
3884 reg = <0x0 0x200>;
3896 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3898 reg = <0x60000 0x4>,
3899 <0x60010 0x4>;
3906 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3910 ranges = <0x0 0x60000 0x1000>;
3912 mailbox10: mailbox@0 {
3914 reg = <0x0 0x200>;
3926 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3928 reg = <0x62000 0x4>,
3929 <0x62010 0x4>;
3936 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3940 ranges = <0x0 0x62000 0x1000>;
3942 mailbox11: mailbox@0 {
3944 reg = <0x0 0x200>;
3956 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3958 reg = <0x64000 0x4>,
3959 <0x64010 0x4>;
3966 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3970 ranges = <0x0 0x64000 0x1000>;
3972 mailbox12: mailbox@0 {
3974 reg = <0x0 0x200>;
3986 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3988 reg = <0x80000 0x4>,
3989 <0x80010 0x4>;
4001 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4005 ranges = <0x0 0x80000 0x20000>;
4007 omap_dwc3_1: omap_dwc3_1@0 {
4009 reg = <0x0 0x10000>;
4014 ranges = <0 0 0x20000>;
4018 reg = <0x10000 0x17000>;
4035 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4037 reg = <0xc0000 0x4>,
4038 <0xc0010 0x4>;
4050 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4054 ranges = <0x0 0xc0000 0x20000>;
4056 omap_dwc3_2: omap_dwc3_2@0 {
4058 reg = <0x0 0x10000>;
4063 ranges = <0 0 0x20000>;
4067 reg = <0x10000 0x17000>;
4085 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4087 reg = <0x100000 0x4>,
4088 <0x100010 0x4>;
4100 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4104 ranges = <0x0 0x100000 0x20000>;
4106 omap_dwc3_3: omap_dwc3_3@0 {
4108 reg = <0x0 0x10000>;
4113 ranges = <0 0 0x20000>;
4118 reg = <0x10000 0x17000>;
4133 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4135 reg = <0x170010 0x4>;
4143 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4147 ranges = <0x0 0x170000 0x10000>;
4151 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4153 reg = <0x190010 0x4>;
4161 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4165 ranges = <0x0 0x190000 0x10000>;
4169 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4171 reg = <0x1b0000 0x4>,
4172 <0x1b0010 0x4>;
4180 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4184 ranges = <0x0 0x1b0000 0x10000>;
4188 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4190 reg = <0x1d0010 0x4>;
4198 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4202 ranges = <0x0 0x1d0000 0x10000>;
4204 vpe: vpe@0 {
4206 reg = <0x0000 0x120>,
4207 <0x0700 0x80>,
4208 <0x5700 0x18>,
4209 <0xd000 0x400>;
4220 &l4_wkup { /* 0x4ae00000 */
4223 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;
4225 reg = <0x4ae00000 0x800>,
4226 <0x4ae00800 0x800>,
4227 <0x4ae01000 0x1000>;
4231 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4232 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4233 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4234 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4236 segment@0 { /* 0x4ae00000 */
4240 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4241 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4242 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4243 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4244 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4245 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4246 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4247 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4248 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4250 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4252 reg = <0x4000 0x4>,
4253 <0x4010 0x4>;
4260 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4264 ranges = <0x0 0x4000 0x1000>;
4266 counter32k: counter@0 {
4268 reg = <0x0 0x40>;
4272 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4274 reg = <0x6000 0x4>;
4278 ranges = <0x0 0x6000 0x2000>;
4280 prm: prm@0 {
4282 reg = <0 0x3000>;
4286 ranges = <0 0 0x3000>;
4290 #size-cells = <0>;
4298 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4300 reg = <0xc000 0x4>;
4304 ranges = <0x0 0xc000 0x1000>;
4306 scm_wkup: scm_conf@0 {
4308 reg = <0 0x1000>;
4313 segment@10000 { /* 0x4ae10000 */
4317 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4318 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4319 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4320 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4321 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4322 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4323 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4324 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4326 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4328 reg = <0x0 0x4>,
4329 <0x10 0x4>,
4330 <0x114 0x4>;
4341 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4346 ranges = <0x0 0x0 0x1000>;
4348 gpio1: gpio@0 {
4350 reg = <0x0 0x200>;
4359 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4361 reg = <0x4000 0x4>,
4362 <0x4010 0x4>,
4363 <0x4014 0x4>;
4373 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4377 ranges = <0x0 0x4000 0x1000>;
4379 wdt2: wdt@0 {
4381 reg = <0x0 0x80>;
4386 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4388 reg = <0x8000 0x4>,
4389 <0x8010 0x4>;
4398 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4402 ranges = <0x0 0x8000 0x1000>;
4404 timer1: timer@0 {
4406 reg = <0x0 0x80>;
4414 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4419 ranges = <0x0 0xc000 0x1000>;
4423 segment@20000 { /* 0x4ae20000 */
4427 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4428 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4429 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4430 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4431 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4432 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4433 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4434 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4435 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4436 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4437 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4438 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4439 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4440 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4442 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4444 reg = <0x0 0x4>,
4445 <0x10 0x4>;
4454 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4458 ranges = <0x0 0x0 0x1000>;
4460 timer12: timer@0 {
4462 reg = <0x0 0x80>;
4469 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4474 ranges = <0x0 0x2000 0x1000>;
4477 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4482 ranges = <0x00000000 0x00006000 0x00001000>,
4483 <0x00001000 0x00007000 0x00000400>,
4484 <0x00002000 0x00008000 0x00000800>,
4485 <0x00002800 0x00008800 0x00000200>,
4486 <0x00002a00 0x00008a00 0x00000100>,
4487 <0x00003000 0x00009000 0x00000100>;
4490 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4492 reg = <0xb050 0x4>,
4493 <0xb054 0x4>,
4494 <0xb058 0x4>;
4505 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4509 ranges = <0x0 0xb000 0x1000>;
4511 uart10: serial@0 {
4513 reg = <0x0 0x100>;
4520 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4525 ranges = <0x0 0xf000 0x1000>;
4529 segment@30000 { /* 0x4ae30000 */
4533 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4534 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4535 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4536 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4537 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4538 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4539 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4540 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4541 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4542 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4543 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4544 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4545 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4547 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4552 ranges = <0x0 0x1000 0x1000>;
4555 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4560 ranges = <0x0 0x3000 0x1000>;
4563 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4568 ranges = <0x0 0x5000 0x1000>;
4571 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4576 ranges = <0x0 0x7000 0x1000>;
4579 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4584 ranges = <0x0 0x9000 0x1000>;
4587 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4589 reg = <0xc020 0x4>;
4591 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4595 ranges = <0x0 0xc000 0x2000>;
4597 dcan1: can@0 {
4599 reg = <0x0 0x2000>;
4600 syscon-raminit = <&scm_conf 0x558 0>;