Lines Matching +full:0 +full:x95800000
15 memory@0 {
17 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
45 reg = <0x0 0x95800000 0x0 0x3800000>;
52 reg = <0x0 0x99000000 0x0 0x4000000>;
59 reg = <0x0 0x9d000000 0x0 0x2000000>;
66 reg = <0x0 0x9f000000 0x0 0x800000>;
135 gpio = <&gpio5 8 0>;
157 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
158 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
164 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
165 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
176 reg = <0x58>;
323 reg = <0x20>;
334 reg = <0x21>;
335 lines-initial-states = <0x1408>;
345 #sound-dai-cells = <0>;
347 reg = <0x19>;
366 reg = <0x26>;
390 pinctrl-0 = <&mmc1_pins_default>;
408 pinctrl-0 = <&mmc2_pins_default>;
421 pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
446 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
447 nand@0,0 {
449 reg = <0 0 4>; /* device IO registers */
451 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
453 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
459 gpmc,sync-clk-ps = <0>;
460 gpmc,cs-on-ns = <0>;
463 gpmc,adv-on-ns = <0>;
474 gpmc,bus-turnaround-ns = <0>;
475 gpmc,cycle2cycle-delay-ns = <0>;
476 gpmc,clk-activation-ns = <0>;
477 gpmc,wr-data-mux-bus-ns = <0>;
484 partition@0 {
486 reg = <0x00000000 0x00020000>;
490 reg = <0x00020000 0x00020000>;
494 reg = <0x00040000 0x00020000>;
498 reg = <0x00060000 0x00020000>;
502 reg = <0x00080000 0x00040000>;
506 reg = <0x000c0000 0x00100000>;
510 reg = <0x001c0000 0x00020000>;
514 reg = <0x001e0000 0x00020000>;
518 reg = <0x00200000 0x00800000>;
522 reg = <0x00a00000 0x0f600000>;
569 pinctrl-0 = <&dcan1_pins_sleep>;