Lines Matching full:rcc
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
265 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
274 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
281 clocks = <&rcc 1 CLK_USART2>;
289 clocks = <&rcc 1 CLK_USART3>;
297 clocks = <&rcc 1 CLK_UART4>;
305 clocks = <&rcc 1 CLK_UART5>;
314 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
315 clocks = <&rcc 1 CLK_I2C1>;
326 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
327 clocks = <&rcc 1 CLK_I2C2>;
338 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
339 clocks = <&rcc 1 CLK_I2C3>;
350 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
351 clocks = <&rcc 1 CLK_I2C4>;
362 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
363 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
372 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
380 resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
381 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
400 clocks = <&rcc 1 CLK_UART7>;
408 clocks = <&rcc 1 CLK_UART8>;
417 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
439 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
460 clocks = <&rcc 1 CLK_USART1>;
468 clocks = <&rcc 1 CLK_USART6>;
476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
487 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
512 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
532 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
546 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
561 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
562 clocks = <&rcc 1 CLK_LCD>;
575 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
579 rcc: rcc@40023800 { label
582 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
586 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
601 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
617 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
627 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
639 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
647 clocks = <&rcc 1 0>;