dts/st/stm32f746.dtsi

53 			#clock-cells = <0>;
55 			clock-frequency = <0>;
59 			#clock-cells = <0>;
65 			#clock-cells = <0>;
71 			#clock-cells = <0>;
80 			#size-cells = <0>;
82 			reg = <0x40000000 0x400>;
83 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 			#size-cells = <0>;
104 			reg = <0x40000400 0x400>;
105 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
124 			#size-cells = <0>;
126 			reg = <0x40000800 0x400>;
127 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
146 			#size-cells = <0>;
148 			reg = <0x40000C00 0x400>;
149 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
168 			#size-cells = <0>;
170 			reg = <0x40001000 0x400>;
171 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
184 			#size-cells = <0>;
186 			reg = <0x40001400 0x400>;
187 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
200 			#size-cells = <0>;
202 			reg = <0x40001800 0x400>;
203 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
222 			reg = <0x40001C00 0x400>;
223 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
236 			reg = <0x40002000 0x400>;
237 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
250 			reg = <0x40002800 0x400>;
256 			st,syscfg = <&pwrcfg 0x00 0x100>;
262 			reg = <0x40003400 0x200>;
266 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
273 			reg = <0x40003600 0x200>;
274 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
279 			reg = <0x40004400 0x400>;
287 			reg = <0x40004800 0x400>;
295 			reg = <0x40004c00 0x400>;
303 			reg = <0x40005000 0x400>;
311 			reg = <0x40005400 0x400>;
317 			#size-cells = <0>;
323 			reg = <0x40005800 0x400>;
329 			#size-cells = <0>;
335 			reg = <0x40005c00 0x400>;
341 			#size-cells = <0>;
347 			reg = <0x40006000 0x400>;
353 			#size-cells = <0>;
359 			reg = <0x40006400 0x200>;
363 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
371 			reg = <0x40006600 0x200>;
372 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
377 			reg = <0x40006800 0x200>;
381 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
389 			reg = <0x40006C00 0x400>;
391 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
398 			reg = <0x40007800 0x400>;
406 			reg = <0x40007c00 0x400>;
414 			#size-cells = <0>;
416 			reg = <0x40010000 0x400>;
417 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
427 			timer@0 {
429 				reg = <0>;
436 			#size-cells = <0>;
438 			reg = <0x40010400 0x400>;
439 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
458 			reg = <0x40011000 0x400>;
466 			reg = <0x40011400 0x400>;
474 			arm,primecell-periphid = <0x00880180>;
475 			reg = <0x40011c00 0x400>;
476 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
485 			arm,primecell-periphid = <0x00880180>;
486 			reg = <0x40012c00 0x400>;
487 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
496 			reg = <0x40013800 0x400>;
503 			reg = <0x40013C00 0x400>;
509 			#size-cells = <0>;
511 			reg = <0x40014000 0x400>;
512 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
531 			reg = <0x40014400 0x400>;
532 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
545 			reg = <0x40014800 0x400>;
546 			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
559 			reg = <0x40016800 0x200>;
569 			reg = <0x40007000 0x400>;
574 			reg = <0x40023000 0x400>;
575 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
583 			reg = <0x40023800 0x400>;
592 			reg = <0x40026000 0x400>;
601 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
608 			reg = <0x40026400 0x400>;
617 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
625 			reg = <0x40040000 0x40000>;
627 			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
637 			reg = <0x50000000 0x40000>;
639 			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
647 	clocks = <&rcc 1 0>;