Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-a7";
34 enable-method = "psci";
40 compatible = "arm,cortex-a7";
42 enable-method = "psci";
48 compatible = "arm,cortex-a7";
50 enable-method = "psci";
56 compatible = "arm,cortex-a7";
58 enable-method = "psci";
63 arm-pmu {
64 compatible = "arm,cortex-a7-pmu";
69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
73 compatible = "arm,psci-1.0";
78 compatible = "arm,armv7-timer";
83 clock-frequency = <24000000>;
87 compatible = "rockchip,display-subsystem";
92 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
94 clock-output-names = "xin24m";
95 #clock-cells = <0>;
99 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
104 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
107 pmu_io_domains: io-domains {
108 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
114 compatible = "rockchip,rv1126-qos", "syscon";
119 compatible = "rockchip,rv1126-qos", "syscon";
124 compatible = "rockchip,rv1126-qos", "syscon";
129 compatible = "rockchip,rv1126-qos", "syscon";
134 compatible = "rockchip,rv1126-qos", "syscon";
139 compatible = "rockchip,rv1126-qos", "syscon";
144 compatible = "rockchip,rv1126-qos", "syscon";
149 compatible = "rockchip,rv1126-qos", "syscon";
153 gic: interrupt-controller@feff0000 {
154 compatible = "arm,gic-400";
155 interrupt-controller;
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
166 pmu: power-management@ff3e0000 {
167 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
170 power: power-controller {
171 compatible = "rockchip,rv1126-power-controller";
172 #power-domain-cells = <1>;
173 #address-cells = <1>;
174 #size-cells = <0>;
176 power-domain@RV1126_PD_NVM {
188 #power-domain-cells = <0>;
191 power-domain@RV1126_PD_SDIO {
196 #power-domain-cells = <0>;
199 power-domain@RV1126_PD_VO {
215 #power-domain-cells = <0>;
221 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
226 clock-names = "i2c", "pclk";
227 pinctrl-names = "default";
228 pinctrl-0 = <&i2c0_xfer>;
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
238 clock-frequency = <24000000>;
240 clock-names = "baudclk", "apb_pclk";
242 dma-names = "tx", "rx";
243 pinctrl-names = "default";
244 pinctrl-0 = <&uart1m0_xfer>;
245 reg-shift = <2>;
246 reg-io-width = <4>;
250 pmucru: clock-controller@ff480000 {
251 compatible = "rockchip,rv1126-pmucru";
254 #clock-cells = <1>;
255 #reset-cells = <1>;
258 cru: clock-controller@ff490000 {
259 compatible = "rockchip,rv1126-cru";
262 clock-names = "xin24m";
264 #clock-cells = <1>;
265 #reset-cells = <1>;
268 dmac: dma-controller@ff4e0000 {
273 #dma-cells = <1>;
274 arm,pl330-periph-burst;
276 clock-names = "apb_pclk";
280 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
283 clock-frequency = <24000000>;
285 clock-names = "baudclk", "apb_pclk";
287 dma-names = "tx", "rx";
288 pinctrl-names = "default";
289 pinctrl-0 = <&uart0_xfer>;
290 reg-shift = <2>;
291 reg-io-width = <4>;
296 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
299 clock-frequency = <24000000>;
301 clock-names = "baudclk", "apb_pclk";
303 dma-names = "tx", "rx";
304 pinctrl-names = "default";
305 pinctrl-0 = <&uart2m1_xfer>;
306 reg-shift = <2>;
307 reg-io-width = <4>;
312 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
315 clock-frequency = <24000000>;
317 clock-names = "baudclk", "apb_pclk";
319 dma-names = "tx", "rx";
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart3m0_xfer>;
322 reg-shift = <2>;
323 reg-io-width = <4>;
328 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
331 clock-frequency = <24000000>;
333 clock-names = "baudclk", "apb_pclk";
335 dma-names = "tx", "rx";
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart4m0_xfer>;
338 reg-shift = <2>;
339 reg-io-width = <4>;
344 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
347 clock-frequency = <24000000>;
349 clock-names = "baudclk", "apb_pclk";
351 dma-names = "tx", "rx";
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart5m0_xfer>;
354 reg-shift = <2>;
355 reg-io-width = <4>;
360 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
363 #io-channel-cells = <1>;
365 clock-names = "saradc", "apb_pclk";
367 reset-names = "saradc-apb";
372 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
376 clock-names = "pclk", "timer";
380 compatible = "rockchip,rv1126-vop";
383 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
385 reset-names = "axi", "ahb", "dclk";
388 power-domains = <&power RV1126_PD_VO>;
392 #address-cells = <1>;
393 #size-cells = <0>;
409 clock-names = "aclk", "iface";
411 #iommu-cells = <0>;
412 power-domains = <&power RV1126_PD_VO>;
417 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
421 interrupt-names = "macirq", "eth_wake_irq";
427 clock-names = "stmmaceth", "mac_clk_rx",
432 reset-names = "stmmaceth";
434 snps,mixed-burst;
437 snps,axi-config = <&stmmac_axi_setup>;
438 snps,mtl-rx-config = <&mtl_rx_setup>;
439 snps,mtl-tx-config = <&mtl_tx_setup>;
443 compatible = "snps,dwmac-mdio";
444 #address-cells = <0x1>;
445 #size-cells = <0x0>;
448 stmmac_axi_setup: stmmac-axi-config {
454 mtl_rx_setup: rx-queues-config {
455 snps,rx-queues-to-use = <1>;
459 mtl_tx_setup: tx-queues-config {
460 snps,tx-queues-to-use = <1>;
466 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
471 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
472 fifo-depth = <0x100>;
473 max-frequency = <200000000>;
474 power-domains = <&power RV1126_PD_NVM>;
479 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
484 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
485 fifo-depth = <0x100>;
486 max-frequency = <200000000>;
491 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
496 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
497 fifo-depth = <0x100>;
498 max-frequency = <200000000>;
499 power-domains = <&power RV1126_PD_SDIO>;
507 assigned-clocks = <&cru SCLK_SFC>;
508 assigned-clock-rates = <80000000>;
509 clock-names = "clk_sfc", "hclk_sfc";
511 power-domains = <&power RV1126_PD_NVM>;
516 compatible = "rockchip,rv1126-pinctrl";
519 #address-cells = <1>;
520 #size-cells = <1>;
524 compatible = "rockchip,gpio-bank";
528 gpio-controller;
529 #gpio-cells = <2>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
535 compatible = "rockchip,gpio-bank";
539 gpio-controller;
540 #gpio-cells = <2>;
541 interrupt-controller;
542 #interrupt-cells = <2>;
546 compatible = "rockchip,gpio-bank";
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 compatible = "rockchip,gpio-bank";
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
568 compatible = "rockchip,gpio-bank";
572 gpio-controller;
573 #gpio-cells = <2>;
574 interrupt-controller;
575 #interrupt-cells = <2>;
580 #include "rv1126-pinctrl.dtsi"