Lines Matching +full:ns +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
32 resets = <&cru SRST_CORE0>;
33 operating-points-v2 = <&cpu0_opp_table>;
34 #cooling-cells = <2>; /* min followed by max */
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 enable-method = "psci";
42 compatible = "arm,cortex-a7";
44 resets = <&cru SRST_CORE1>;
45 operating-points-v2 = <&cpu0_opp_table>;
46 #cooling-cells = <2>; /* min followed by max */
47 enable-method = "psci";
52 compatible = "arm,cortex-a7";
54 resets = <&cru SRST_CORE2>;
55 operating-points-v2 = <&cpu0_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
57 enable-method = "psci";
62 compatible = "arm,cortex-a7";
64 resets = <&cru SRST_CORE3>;
65 operating-points-v2 = <&cpu0_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
67 enable-method = "psci";
71 cpu0_opp_table: opp-table-0 {
72 compatible = "operating-points-v2";
73 opp-shared;
75 opp-408000000 {
76 opp-hz = /bits/ 64 <408000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
79 opp-suspend;
81 opp-600000000 {
82 opp-hz = /bits/ 64 <600000000>;
83 opp-microvolt = <975000>;
85 opp-816000000 {
86 opp-hz = /bits/ 64 <816000000>;
87 opp-microvolt = <1000000>;
89 opp-1008000000 {
90 opp-hz = /bits/ 64 <1008000000>;
91 opp-microvolt = <1175000>;
93 opp-1200000000 {
94 opp-hz = /bits/ 64 <1200000000>;
95 opp-microvolt = <1275000>;
99 arm-pmu {
100 compatible = "arm,cortex-a7-pmu";
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
114 compatible = "arm,armv7-timer";
115 arm,cpu-registers-not-fw-configured;
120 clock-frequency = <24000000>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
127 #clock-cells = <0>;
130 display_subsystem: display-subsystem {
131 compatible = "rockchip,display-subsystem";
136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
139 clock-names = "i2s_clk", "i2s_hclk";
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
142 dma-names = "tx", "rx";
143 pinctrl-names = "default";
144 pinctrl-0 = <&i2s1_bus>;
149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
152 clock-names = "i2s_clk", "i2s_hclk";
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
155 dma-names = "tx", "rx";
160 compatible = "rockchip,rk3228-spdif";
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
164 clock-names = "mclk", "hclk";
166 dma-names = "tx";
167 pinctrl-names = "default";
168 pinctrl-0 = <&spdif_tx>;
173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
176 clock-names = "i2s_clk", "i2s_hclk";
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
179 dma-names = "tx", "rx";
184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
186 #address-cells = <1>;
187 #size-cells = <1>;
189 io_domains: io-domains {
190 compatible = "rockchip,rk3228-io-voltage-domain";
194 power: power-controller {
195 compatible = "rockchip,rk3228-power-controller";
196 #power-domain-cells = <1>;
197 #address-cells = <1>;
198 #size-cells = <0>;
200 power-domain@RK3228_PD_VIO {
202 clocks = <&cru ACLK_HDCP>,
203 <&cru SCLK_HDCP>,
204 <&cru ACLK_IEP>,
205 <&cru HCLK_IEP>,
206 <&cru ACLK_RGA>,
207 <&cru HCLK_RGA>,
208 <&cru SCLK_RGA>;
213 #power-domain-cells = <0>;
216 power-domain@RK3228_PD_VOP {
218 clocks =<&cru ACLK_VOP>,
219 <&cru DCLK_VOP>,
220 <&cru HCLK_VOP>;
222 #power-domain-cells = <0>;
225 power-domain@RK3228_PD_VPU {
227 clocks = <&cru ACLK_VPU>,
228 <&cru HCLK_VPU>;
230 #power-domain-cells = <0>;
233 power-domain@RK3228_PD_RKVDEC {
235 clocks = <&cru ACLK_RKVDEC>,
236 <&cru HCLK_RKVDEC>,
237 <&cru SCLK_VDEC_CABAC>,
238 <&cru SCLK_VDEC_CORE>;
241 #power-domain-cells = <0>;
244 power-domain@RK3228_PD_GPU {
246 clocks = <&cru ACLK_GPU>;
248 #power-domain-cells = <0>;
253 compatible = "rockchip,rk3228-usb2phy";
255 clocks = <&cru SCLK_OTGPHY0>;
256 clock-names = "phyclk";
257 clock-output-names = "usb480m_phy0";
258 #clock-cells = <0>;
261 u2phy0_otg: otg-port {
265 interrupt-names = "otg-bvalid", "otg-id",
267 #phy-cells = <0>;
271 u2phy0_host: host-port {
273 interrupt-names = "linestate";
274 #phy-cells = <0>;
280 compatible = "rockchip,rk3228-usb2phy";
282 clocks = <&cru SCLK_OTGPHY1>;
283 clock-names = "phyclk";
284 clock-output-names = "usb480m_phy1";
285 #clock-cells = <0>;
288 u2phy1_otg: otg-port {
290 interrupt-names = "linestate";
291 #phy-cells = <0>;
295 u2phy1_host: host-port {
297 interrupt-names = "linestate";
298 #phy-cells = <0>;
305 compatible = "snps,dw-apb-uart";
308 clock-frequency = <24000000>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
313 reg-shift = <2>;
314 reg-io-width = <4>;
319 compatible = "snps,dw-apb-uart";
322 clock-frequency = <24000000>;
323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
324 clock-names = "baudclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_xfer>;
327 reg-shift = <2>;
328 reg-io-width = <4>;
333 compatible = "snps,dw-apb-uart";
336 clock-frequency = <24000000>;
337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
338 clock-names = "baudclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_xfer>;
341 reg-shift = <2>;
342 reg-io-width = <4>;
347 compatible = "rockchip,rk3228-efuse";
349 clocks = <&cru PCLK_EFUSE_256>;
350 clock-names = "pclk_efuse";
351 #address-cells = <1>;
352 #size-cells = <1>;
364 compatible = "rockchip,rk3228-i2c";
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clock-names = "i2c";
370 clocks = <&cru PCLK_I2C0>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c0_xfer>;
377 compatible = "rockchip,rk3228-i2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 clock-names = "i2c";
383 clocks = <&cru PCLK_I2C1>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c1_xfer>;
390 compatible = "rockchip,rk3228-i2c";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clock-names = "i2c";
396 clocks = <&cru PCLK_I2C2>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2c2_xfer>;
403 compatible = "rockchip,rk3228-i2c";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 clock-names = "i2c";
409 clocks = <&cru PCLK_I2C3>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c3_xfer>;
416 compatible = "rockchip,rk3228-spi";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
422 clock-names = "spiclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
432 clocks = <&cru PCLK_CPU>;
437 compatible = "rockchip,rk3288-pwm";
439 #pwm-cells = <3>;
440 clocks = <&cru PCLK_PWM>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm0_pin>;
447 compatible = "rockchip,rk3288-pwm";
449 #pwm-cells = <3>;
450 clocks = <&cru PCLK_PWM>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pwm1_pin>;
457 compatible = "rockchip,rk3288-pwm";
459 #pwm-cells = <3>;
460 clocks = <&cru PCLK_PWM>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm2_pin>;
467 compatible = "rockchip,rk3288-pwm";
469 #pwm-cells = <2>;
470 clocks = <&cru PCLK_PWM>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm3_pin>;
477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
480 clocks = <&cru PCLK_TIMER>, <&xin24m>;
481 clock-names = "pclk", "timer";
484 cru: clock-controller@110e0000 { label
485 compatible = "rockchip,rk3228-cru";
488 clock-names = "xin24m";
490 #clock-cells = <1>;
491 #reset-cells = <1>;
492 assigned-clocks =
493 <&cru PLL_GPLL>, <&cru ARMCLK>,
494 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
495 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
496 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
497 <&cru PCLK_CPU>;
498 assigned-clock-rates =
506 pdma: dma-controller@110f0000 {
511 #dma-cells = <1>;
512 arm,pl330-periph-burst;
513 clocks = <&cru ACLK_DMAC>;
514 clock-names = "apb_pclk";
517 thermal-zones {
518 cpu_thermal: cpu-thermal {
519 polling-delay-passive = <100>; /* milliseconds */
520 polling-delay = <5000>; /* milliseconds */
522 thermal-sensors = <&tsadc 0>;
542 cooling-maps {
545 cooling-device =
553 cooling-device =
564 compatible = "rockchip,rk3228-tsadc";
567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
568 clock-names = "tsadc", "apb_pclk";
569 assigned-clocks = <&cru SCLK_TSADC>;
570 assigned-clock-rates = <32768>;
571 resets = <&cru SRST_TSADC>;
572 reset-names = "tsadc-apb";
573 pinctrl-names = "init", "default", "sleep";
574 pinctrl-0 = <&otp_pin>;
575 pinctrl-1 = <&otp_out>;
576 pinctrl-2 = <&otp_pin>;
577 #thermal-sensor-cells = <1>;
578 rockchip,hw-tshut-temp = <95000>;
582 hdmi_phy: hdmi-phy@12030000 {
583 compatible = "rockchip,rk3228-hdmi-phy";
585 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
586 clock-names = "sysclk", "refoclk", "refpclk";
587 #clock-cells = <0>;
588 clock-output-names = "hdmiphy_phy";
589 #phy-cells = <0>;
594 compatible = "rockchip,rk3228-mali", "arm,mali-400";
602 interrupt-names = "gp",
608 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
609 clock-names = "bus", "core";
610 power-domains = <&power RK3228_PD_GPU>;
611 resets = <&cru SRST_GPU_A>;
615 vpu: video-codec@20020000 {
616 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
620 interrupt-names = "vepu", "vdpu";
621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
622 clock-names = "aclk", "hclk";
624 power-domains = <&power RK3228_PD_VPU>;
631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
632 clock-names = "aclk", "iface";
633 power-domains = <&power RK3228_PD_VPU>;
634 #iommu-cells = <0>;
637 vdec: video-codec@20030000 {
638 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
641 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
642 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
643 clock-names = "axi", "ahb", "cabac", "core";
644 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
645 assigned-clock-rates = <300000000>, <300000000>;
647 power-domains = <&power RK3228_PD_RKVDEC>;
654 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
655 clock-names = "aclk", "iface";
656 power-domains = <&power RK3228_PD_RKVDEC>;
657 #iommu-cells = <0>;
661 compatible = "rockchip,rk3228-vop";
664 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
665 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
666 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
667 reset-names = "axi", "ahb", "dclk";
669 power-domains = <&power RK3228_PD_VOP>;
673 #address-cells = <1>;
674 #size-cells = <0>;
678 remote-endpoint = <&hdmi_in_vop>;
687 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
688 clock-names = "aclk", "iface";
689 power-domains = <&power RK3228_PD_VOP>;
690 #iommu-cells = <0>;
695 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
699 clock-names = "aclk", "hclk", "sclk";
700 power-domains = <&power RK3228_PD_VIO>;
701 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
702 reset-names = "core", "axi", "ahb";
709 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
710 clock-names = "aclk", "iface";
711 power-domains = <&power RK3228_PD_VIO>;
712 #iommu-cells = <0>;
717 compatible = "rockchip,rk3228-dw-hdmi";
719 reg-io-width = <4>;
721 assigned-clocks = <&cru SCLK_HDMI_PHY>;
722 assigned-clock-parents = <&hdmi_phy>;
723 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
724 clock-names = "iahb", "isfr", "cec";
725 pinctrl-names = "default";
726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
727 resets = <&cru SRST_HDMI_P>;
728 reset-names = "hdmi";
730 phy-names = "hdmi";
735 #address-cells = <1>;
736 #size-cells = <0>;
742 remote-endpoint = <&vop_out_hdmi>;
753 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
756 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
757 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
758 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
759 fifo-depth = <0x100>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
766 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
769 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
770 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
771 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
772 fifo-depth = <0x100>;
773 pinctrl-names = "default";
774 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
779 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
782 clock-frequency = <37500000>;
783 max-frequency = <37500000>;
784 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
785 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
786 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
787 bus-width = <8>;
788 rockchip,default-sample-phase = <158>;
789 fifo-depth = <0x100>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
792 resets = <&cru SRST_EMMC>;
793 reset-names = "reset";
798 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
802 clocks = <&cru HCLK_OTG>;
803 clock-names = "otg";
805 g-np-tx-fifo-size = <16>;
806 g-rx-fifo-size = <280>;
807 g-tx-fifo-size = <256 128 128 64 32 16>;
809 phy-names = "usb2-phy";
814 compatible = "generic-ehci";
817 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
819 phy-names = "usb";
824 compatible = "generic-ohci";
827 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
829 phy-names = "usb";
834 compatible = "generic-ehci";
837 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
839 phy-names = "usb";
844 compatible = "generic-ohci";
847 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
849 phy-names = "usb";
854 compatible = "generic-ehci";
857 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
859 phy-names = "usb";
864 compatible = "generic-ohci";
867 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
869 phy-names = "usb";
874 compatible = "rockchip,rk3228-gmac";
877 interrupt-names = "macirq";
878 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
879 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
880 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
881 <&cru PCLK_GMAC>;
882 clock-names = "stmmaceth", "mac_clk_rx",
886 resets = <&cru SRST_GMAC>;
887 reset-names = "stmmaceth";
893 compatible = "rockchip,rk3228-qos", "syscon";
898 compatible = "rockchip,rk3228-qos", "syscon";
903 compatible = "rockchip,rk3228-qos", "syscon";
908 compatible = "rockchip,rk3228-qos", "syscon";
913 compatible = "rockchip,rk3228-qos", "syscon";
918 compatible = "rockchip,rk3228-qos", "syscon";
923 compatible = "rockchip,rk3228-qos", "syscon";
928 compatible = "rockchip,rk3228-qos", "syscon";
933 compatible = "rockchip,rk3228-qos", "syscon";
937 gic: interrupt-controller@32010000 {
938 compatible = "arm,gic-400";
939 interrupt-controller;
940 #interrupt-cells = <3>;
941 #address-cells = <0>;
951 compatible = "rockchip,rk3228-pinctrl";
953 #address-cells = <1>;
954 #size-cells = <1>;
958 compatible = "rockchip,gpio-bank";
961 clocks = <&cru PCLK_GPIO0>;
963 gpio-controller;
964 #gpio-cells = <2>;
966 interrupt-controller;
967 #interrupt-cells = <2>;
971 compatible = "rockchip,gpio-bank";
974 clocks = <&cru PCLK_GPIO1>;
976 gpio-controller;
977 #gpio-cells = <2>;
979 interrupt-controller;
980 #interrupt-cells = <2>;
984 compatible = "rockchip,gpio-bank";
987 clocks = <&cru PCLK_GPIO2>;
989 gpio-controller;
990 #gpio-cells = <2>;
992 interrupt-controller;
993 #interrupt-cells = <2>;
997 compatible = "rockchip,gpio-bank";
1000 clocks = <&cru PCLK_GPIO3>;
1002 gpio-controller;
1003 #gpio-cells = <2>;
1005 interrupt-controller;
1006 #interrupt-cells = <2>;
1009 pcfg_pull_up: pcfg-pull-up {
1010 bias-pull-up;
1013 pcfg_pull_down: pcfg-pull-down {
1014 bias-pull-down;
1017 pcfg_pull_none: pcfg-pull-none {
1018 bias-disable;
1021 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1022 drive-strength = <12>;
1026 sdmmc_clk: sdmmc-clk {
1030 sdmmc_cmd: sdmmc-cmd {
1034 sdmmc_bus4: sdmmc-bus4 {
1043 sdio_clk: sdio-clk {
1047 sdio_cmd: sdio-cmd {
1051 sdio_bus4: sdio-bus4 {
1060 emmc_clk: emmc-clk {
1064 emmc_cmd: emmc-cmd {
1068 emmc_bus8: emmc-bus8 {
1081 rgmii_pins: rgmii-pins {
1099 rmii_pins: rmii-pins {
1112 phy_pins: phy-pins {
1119 hdmi_hpd: hdmi-hpd {
1123 hdmii2c_xfer: hdmii2c-xfer {
1128 hdmi_cec: hdmi-cec {
1134 i2c0_xfer: i2c0-xfer {
1141 i2c1_xfer: i2c1-xfer {
1148 i2c2_xfer: i2c2-xfer {
1155 i2c3_xfer: i2c3-xfer {
1162 spi0_clk: spi0-clk {
1165 spi0_cs0: spi0-cs0 {
1168 spi0_tx: spi0-tx {
1171 spi0_rx: spi0-rx {
1174 spi0_cs1: spi0-cs1 {
1180 spi1_clk: spi1-clk {
1183 spi1_cs0: spi1-cs0 {
1186 spi1_rx: spi1-rx {
1189 spi1_tx: spi1-tx {
1192 spi1_cs1: spi1-cs1 {
1198 i2s1_bus: i2s1-bus {
1212 pwm0_pin: pwm0-pin {
1218 pwm1_pin: pwm1-pin {
1224 pwm2_pin: pwm2-pin {
1230 pwm3_pin: pwm3-pin {
1236 spdif_tx: spdif-tx {
1242 otp_pin: otp-pin {
1246 otp_out: otp-out {
1252 uart0_xfer: uart0-xfer {
1257 uart0_cts: uart0-cts {
1261 uart0_rts: uart0-rts {
1267 uart1_xfer: uart1-xfer {
1272 uart1_cts: uart1-cts {
1276 uart1_rts: uart1-rts {
1282 uart2_xfer: uart2-xfer {
1287 uart21_xfer: uart21-xfer {
1292 uart2_cts: uart2-cts {
1296 uart2_rts: uart2-rts {