Lines Matching +full:0 +full:x110a0000
26 #size-cells = <0>;
31 reg = <0xf00>;
43 reg = <0xf01>;
53 reg = <0xf02>;
63 reg = <0xf03>;
71 cpu0_opp_table: opp-table-0 {
127 #clock-cells = <0>;
137 reg = <0x100b0000 0x4000>;
144 pinctrl-0 = <&i2s1_bus>;
150 reg = <0x100c0000 0x4000>;
161 reg = <0x100d0000 0x1000>;
168 pinctrl-0 = <&spdif_tx>;
174 reg = <0x100e0000 0x4000>;
178 dmas = <&pdma 0>, <&pdma 1>;
185 reg = <0x11000000 0x1000>;
198 #size-cells = <0>;
213 #power-domain-cells = <0>;
222 #power-domain-cells = <0>;
230 #power-domain-cells = <0>;
241 #power-domain-cells = <0>;
248 #power-domain-cells = <0>;
254 reg = <0x0760 0x0c>;
258 #clock-cells = <0>;
267 #phy-cells = <0>;
274 #phy-cells = <0>;
281 reg = <0x0800 0x0c>;
285 #clock-cells = <0>;
291 #phy-cells = <0>;
298 #phy-cells = <0>;
306 reg = <0x11010000 0x100>;
312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
320 reg = <0x11020000 0x100>;
326 pinctrl-0 = <&uart1_xfer>;
334 reg = <0x11030000 0x100>;
340 pinctrl-0 = <&uart2_xfer>;
348 reg = <0x11040000 0x20>;
356 reg = <0x7 0x10>;
359 reg = <0x17 0x1>;
365 reg = <0x11050000 0x1000>;
368 #size-cells = <0>;
372 pinctrl-0 = <&i2c0_xfer>;
378 reg = <0x11060000 0x1000>;
381 #size-cells = <0>;
385 pinctrl-0 = <&i2c1_xfer>;
391 reg = <0x11070000 0x1000>;
394 #size-cells = <0>;
398 pinctrl-0 = <&i2c2_xfer>;
404 reg = <0x11080000 0x1000>;
407 #size-cells = <0>;
411 pinctrl-0 = <&i2c3_xfer>;
417 reg = <0x11090000 0x1000>;
420 #size-cells = <0>;
424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
430 reg = <0x110a0000 0x100>;
438 reg = <0x110b0000 0x10>;
442 pinctrl-0 = <&pwm0_pin>;
448 reg = <0x110b0010 0x10>;
452 pinctrl-0 = <&pwm1_pin>;
458 reg = <0x110b0020 0x10>;
462 pinctrl-0 = <&pwm2_pin>;
468 reg = <0x110b0030 0x10>;
472 pinctrl-0 = <&pwm3_pin>;
478 reg = <0x110c0000 0x20>;
486 reg = <0x110e0000 0x1000>;
508 reg = <0x110f0000 0x4000>;
509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
522 thermal-sensors = <&tsadc 0>;
565 reg = <0x11150000 0x100>;
574 pinctrl-0 = <&otp_pin>;
584 reg = <0x12030000 0x10000>;
587 #clock-cells = <0>;
589 #phy-cells = <0>;
595 reg = <0x20000000 0x10000>;
617 reg = <0x20020000 0x800>;
629 reg = <0x20020800 0x100>;
634 #iommu-cells = <0>;
639 reg = <0x20030000 0x480>;
652 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
657 #iommu-cells = <0>;
662 reg = <0x20050000 0x1ffc>;
674 #size-cells = <0>;
676 vop_out_hdmi: endpoint@0 {
677 reg = <0>;
685 reg = <0x20053f00 0x100>;
690 #iommu-cells = <0>;
696 reg = <0x20060000 0x1000>;
707 reg = <0x20070800 0x100>;
712 #iommu-cells = <0>;
718 reg = <0x200a0000 0x20000>;
726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
736 #size-cells = <0>;
738 hdmi_in: port@0 {
739 reg = <0>;
754 reg = <0x30000000 0x4000>;
759 fifo-depth = <0x100>;
761 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
767 reg = <0x30010000 0x4000>;
772 fifo-depth = <0x100>;
774 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
780 reg = <0x30020000 0x4000>;
789 fifo-depth = <0x100>;
791 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
800 reg = <0x30040000 0x40000>;
815 reg = <0x30080000 0x20000>;
825 reg = <0x300a0000 0x20000>;
835 reg = <0x300c0000 0x20000>;
845 reg = <0x300e0000 0x20000>;
855 reg = <0x30100000 0x20000>;
865 reg = <0x30120000 0x20000>;
875 reg = <0x30200000 0x10000>;
894 reg = <0x31030080 0x20>;
899 reg = <0x31030100 0x20>;
904 reg = <0x31030180 0x20>;
909 reg = <0x31030200 0x20>;
914 reg = <0x31040000 0x20>;
919 reg = <0x31050000 0x20>;
924 reg = <0x31060000 0x20>;
929 reg = <0x31070000 0x20>;
934 reg = <0x31070080 0x20>;
941 #address-cells = <0>;
943 reg = <0x32011000 0x1000>,
944 <0x32012000 0x2000>,
945 <0x32014000 0x2000>,
946 <0x32016000 0x2000>;
959 reg = <0x11110000 0x100>;
972 reg = <0x11120000 0x100>;
985 reg = <0x11130000 0x100>;
998 reg = <0x11140000 0x100>;
1120 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1124 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1125 <0 RK_PA7 2 &pcfg_pull_none>;
1129 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1135 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1136 <0 RK_PA1 1 &pcfg_pull_none>;
1142 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1143 <0 RK_PA3 1 &pcfg_pull_none>;
1156 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1157 <0 RK_PA7 1 &pcfg_pull_none>;
1163 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1166 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1169 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1172 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1181 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1199 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1200 <0 RK_PB1 1 &pcfg_pull_none>,
1201 <0 RK_PB3 1 &pcfg_pull_none>,
1202 <0 RK_PB4 1 &pcfg_pull_none>,
1203 <0 RK_PB5 1 &pcfg_pull_none>,
1204 <0 RK_PB6 1 &pcfg_pull_none>,
1219 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1243 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1247 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1262 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1293 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1297 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;