Lines Matching +full:emmc +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
18 arm-pmu {
19 compatible = "arm,cortex-a7-pmu";
24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
37 operating-points = <
41 #cooling-cells = <2>; /* min followed by max */
46 compatible = "arm,cortex-a7";
52 compatible = "arm,cortex-a7";
58 compatible = "arm,cortex-a7";
64 compatible = "arm,armv7-timer";
69 arm,cpu-registers-not-fw-configured;
70 clock-frequency = <24000000>;
74 compatible = "fixed-clock";
75 clock-frequency = <24000000>;
76 clock-output-names = "xin24m";
77 #clock-cells = <0>;
81 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
85 gic: interrupt-controller@10139000 {
86 compatible = "arm,cortex-a7-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 #address-cells = <0>;
98 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
102 clock-names = "otg";
105 phy-names = "usb2-phy";
110 compatible = "generic-ehci";
114 phy-names = "usb";
119 compatible = "generic-ohci";
123 phy-names = "usb";
128 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
133 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
135 dma-names = "rx-tx";
136 fifo-depth = <256>;
137 max-frequency = <150000000>;
139 reset-names = "reset";
144 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
149 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
151 dma-names = "rx-tx";
152 fifo-depth = <256>;
153 max-frequency = <150000000>;
155 reset-names = "reset";
159 emmc: mmc@1021c000 { label
160 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
165 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
167 dma-names = "rx-tx";
168 fifo-depth = <256>;
169 max-frequency = <150000000>;
171 reset-names = "reset";
175 nfc: nand-controller@10500000 {
176 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
180 clock-names = "ahb", "nfc";
181 pinctrl-names = "default";
182 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
187 cru: clock-controller@20000000 {
188 compatible = "rockchip,rk3128-cru";
191 clock-names = "xin24m";
193 #clock-cells = <1>;
194 #reset-cells = <1>;
195 assigned-clocks = <&cru PLL_GPLL>;
196 assigned-clock-rates = <594000000>;
200 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
202 #address-cells = <1>;
203 #size-cells = <1>;
206 compatible = "rockchip,rk3128-usb2phy";
209 clock-names = "phyclk";
210 clock-output-names = "usb480m_phy";
211 #clock-cells = <0>;
214 usb2phy_host: host-port {
216 interrupt-names = "linestate";
217 #phy-cells = <0>;
221 usb2phy_otg: otg-port {
225 interrupt-names = "otg-bvalid", "otg-id",
227 #phy-cells = <0>;
234 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
238 clock-names = "pclk", "timer";
242 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
246 clock-names = "pclk", "timer";
250 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
254 clock-names = "pclk", "timer";
258 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
262 clock-names = "pclk", "timer";
266 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
270 clock-names = "pclk", "timer";
274 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
278 clock-names = "pclk", "timer";
282 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
290 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pwm0_pin>;
295 #pwm-cells = <3>;
300 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
303 pinctrl-names = "default";
304 pinctrl-0 = <&pwm1_pin>;
305 #pwm-cells = <3>;
310 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
313 pinctrl-names = "default";
314 pinctrl-0 = <&pwm2_pin>;
315 #pwm-cells = <3>;
320 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pwm3_pin>;
325 #pwm-cells = <3>;
330 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
333 clock-names = "i2c";
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c1_xfer>;
337 #address-cells = <1>;
338 #size-cells = <0>;
343 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
346 clock-names = "i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c2_xfer>;
350 #address-cells = <1>;
351 #size-cells = <0>;
356 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
359 clock-names = "i2c";
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c3_xfer>;
363 #address-cells = <1>;
364 #size-cells = <0>;
369 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
372 clock-frequency = <24000000>;
374 clock-names = "baudclk", "apb_pclk";
376 dma-names = "tx", "rx";
377 pinctrl-names = "default";
378 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
379 reg-io-width = <4>;
380 reg-shift = <2>;
385 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
388 clock-frequency = <24000000>;
390 clock-names = "baudclk", "apb_pclk";
392 dma-names = "tx", "rx";
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart1_xfer>;
395 reg-io-width = <4>;
396 reg-shift = <2>;
401 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
404 clock-frequency = <24000000>;
406 clock-names = "baudclk", "apb_pclk";
408 dma-names = "tx", "rx";
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart2_xfer>;
411 reg-io-width = <4>;
412 reg-shift = <2>;
421 clock-names = "saradc", "apb_pclk";
423 reset-names = "saradc-apb";
424 #io-channel-cells = <1>;
429 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
432 clock-names = "i2c";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c0_xfer>;
436 #address-cells = <1>;
437 #size-cells = <0>;
442 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
446 clock-names = "spiclk", "apb_pclk";
448 dma-names = "tx", "rx";
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
451 #address-cells = <1>;
452 #size-cells = <0>;
456 pdma: dma-controller@20078000 {
461 arm,pl330-broken-no-flushp;
462 arm,pl330-periph-burst;
464 clock-names = "apb_pclk";
465 #dma-cells = <1>;
469 compatible = "rockchip,rk3128-pinctrl";
471 #address-cells = <1>;
472 #size-cells = <1>;
476 compatible = "rockchip,gpio-bank";
480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
487 compatible = "rockchip,gpio-bank";
491 gpio-controller;
492 #gpio-cells = <2>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
498 compatible = "rockchip,gpio-bank";
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
509 compatible = "rockchip,gpio-bank";
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
519 pcfg_pull_default: pcfg-pull-default {
520 bias-pull-pin-default;
523 pcfg_pull_none: pcfg-pull-none {
524 bias-disable;
527 emmc {
528 emmc_clk: emmc-clk {
529 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
532 emmc_cmd: emmc-cmd {
533 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
536 emmc_cmd1: emmc-cmd1 {
537 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
540 emmc_pwr: emmc-pwr {
541 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
544 emmc_bus1: emmc-bus1 {
545 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
548 emmc_bus4: emmc-bus4 {
549 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
555 emmc_bus8: emmc-bus8 {
556 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
568 rgmii_pins: rgmii-pins {
569 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
586 rmii_pins: rmii-pins {
587 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
601 hdmii2c_xfer: hdmii2c-xfer {
602 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
606 hdmi_hpd: hdmi-hpd {
607 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
610 hdmi_cec: hdmi-cec {
611 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
616 i2c0_xfer: i2c0-xfer {
617 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
623 i2c1_xfer: i2c1-xfer {
624 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
630 i2c2_xfer: i2c2-xfer {
631 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
637 i2c3_xfer: i2c3-xfer {
638 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
644 i2s_bus: i2s-bus {
645 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
653 i2s1_bus: i2s1-bus {
654 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
664 lcdc_dclk: lcdc-dclk {
665 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
668 lcdc_den: lcdc-den {
669 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
672 lcdc_hsync: lcdc-hsync {
673 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
676 lcdc_vsync: lcdc-vsync {
677 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
680 lcdc_rgb24: lcdc-rgb24 {
681 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
699 flash_ale: flash-ale {
700 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
703 flash_cle: flash-cle {
704 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
707 flash_wrn: flash-wrn {
708 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
711 flash_rdn: flash-rdn {
712 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
715 flash_rdy: flash-rdy {
716 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
719 flash_cs0: flash-cs0 {
720 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
723 flash_dqs: flash-dqs {
724 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
727 flash_bus8: flash-bus8 {
728 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
740 pwm0_pin: pwm0-pin {
741 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
746 pwm1_pin: pwm1-pin {
747 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
752 pwm2_pin: pwm2-pin {
753 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
758 pwm3_pin: pwm3-pin {
759 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
764 sdio_clk: sdio-clk {
765 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
768 sdio_cmd: sdio-cmd {
769 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
772 sdio_pwren: sdio-pwren {
773 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
776 sdio_bus4: sdio-bus4 {
777 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
785 sdmmc_clk: sdmmc-clk {
786 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
789 sdmmc_cmd: sdmmc-cmd {
790 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
793 sdmmc_wp: sdmmc-wp {
794 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
797 sdmmc_pwren: sdmmc-pwren {
798 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
801 sdmmc_bus4: sdmmc-bus4 {
802 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
810 spdif_tx: spdif-tx {
811 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
816 spi0_clk: spi0-clk {
817 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
820 spi0_cs0: spi0-cs0 {
821 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
824 spi0_tx: spi0-tx {
825 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
828 spi0_rx: spi0-rx {
829 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
832 spi0_cs1: spi0-cs1 {
833 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
836 spi1_clk: spi1-clk {
837 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
840 spi1_cs0: spi1-cs0 {
841 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
844 spi1_tx: spi1-tx {
845 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
848 spi1_rx: spi1-rx {
849 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
852 spi1_cs1: spi1-cs1 {
853 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
856 spi2_clk: spi2-clk {
857 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
860 spi2_cs0: spi2-cs0 {
861 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
864 spi2_tx: spi2-tx {
865 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
868 spi2_rx: spi2-rx {
869 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
874 uart0_xfer: uart0-xfer {
875 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
879 uart0_cts: uart0-cts {
880 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
883 uart0_rts: uart0-rts {
884 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
889 uart1_xfer: uart1-xfer {
890 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
894 uart1_cts: uart1-cts {
895 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
898 uart1_rts: uart1-rts {
899 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
904 uart2_xfer: uart2-xfer {
905 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
909 uart2_cts: uart2-cts {
910 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
913 uart2_rts: uart2-rts {
914 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;