dts/rockchip/rk3066a.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
17 		#address-cells = <1>;
18 		#size-cells = <0>;
19 		enable-method = "rockchip,rk3066-smp";
23 			compatible = "arm,cortex-a9";
24 			next-level-cache = <&L2>;
26 			operating-points =
35 			clock-latency = <40000>;
40 			compatible = "arm,cortex-a9";
41 			next-level-cache = <&L2>;
46 	display-subsystem {
47 		compatible = "rockchip,display-subsystem";
52 		compatible = "mmio-sram";
54 		#address-cells = <1>;
55 		#size-cells = <1>;
58 		smp-sram@0 {
59 			compatible = "rockchip,rk3066-smp-sram";
65 		compatible = "rockchip,rk3066-vop";
71 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
72 		power-domains = <&power RK3066_PD_VIO>;
76 		reset-names = "axi", "ahb", "dclk";
80 			#address-cells = <1>;
81 			#size-cells = <0>;
85 				remote-endpoint = <&hdmi_in_vop0>;
91 		compatible = "rockchip,rk3066-vop";
97 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
98 		power-domains = <&power RK3066_PD_VIO>;
102 		reset-names = "axi", "ahb", "dclk";
106 			#address-cells = <1>;
107 			#size-cells = <0>;
111 				remote-endpoint = <&hdmi_in_vop1>;
117 		compatible = "rockchip,rk3066-hdmi";
121 		clock-names = "hclk";
122 		pinctrl-names = "default";
123 		pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
124 		power-domains = <&power RK3066_PD_VIO>;
126 		#sound-dai-cells = <0>;
130 			#address-cells = <1>;
131 			#size-cells = <0>;
135 				#address-cells = <1>;
136 				#size-cells = <0>;
140 					remote-endpoint = <&vop0_out_hdmi>;
145 					remote-endpoint = <&vop1_out_hdmi>;
156 		compatible = "rockchip,rk3066-i2s";
159 		pinctrl-names = "default";
160 		pinctrl-0 = <&i2s0_bus>;
162 		clock-names = "i2s_clk", "i2s_hclk";
164 		dma-names = "tx", "rx";
165 		rockchip,playback-channels = <8>;
166 		rockchip,capture-channels = <2>;
167 		#sound-dai-cells = <0>;
172 		compatible = "rockchip,rk3066-i2s";
175 		pinctrl-names = "default";
176 		pinctrl-0 = <&i2s1_bus>;
178 		clock-names = "i2s_clk", "i2s_hclk";
180 		dma-names = "tx", "rx";
181 		rockchip,playback-channels = <2>;
182 		rockchip,capture-channels = <2>;
183 		#sound-dai-cells = <0>;
188 		compatible = "rockchip,rk3066-i2s";
191 		pinctrl-names = "default";
192 		pinctrl-0 = <&i2s2_bus>;
194 		clock-names = "i2s_clk", "i2s_hclk";
196 		dma-names = "tx", "rx";
197 		rockchip,playback-channels = <2>;
198 		rockchip,capture-channels = <2>;
199 		#sound-dai-cells = <0>;
203 	cru: clock-controller@20000000 {
204 		compatible = "rockchip,rk3066a-cru";
207 		clock-names = "xin24m";
209 		#clock-cells = <1>;
210 		#reset-cells = <1>;
211 		assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
215 		assigned-clock-rates = <400000000>, <594000000>,
222 		compatible = "snps,dw-apb-timer";
226 		clock-names = "timer", "pclk";
230 		compatible = "rockchip,rk3066a-efuse";
232 		#address-cells = <1>;
233 		#size-cells = <1>;
235 		clock-names = "pclk_efuse";
243 		compatible = "snps,dw-apb-timer";
247 		clock-names = "timer", "pclk";
251 		compatible = "snps,dw-apb-timer";
255 		clock-names = "timer", "pclk";
259 		compatible = "rockchip,rk3066-tsadc";
262 		clock-names = "saradc", "apb_pclk";
264 		#io-channel-cells = <1>;
266 		reset-names = "saradc-apb";
271 		compatible = "rockchip,rk3066a-pinctrl";
273 		#address-cells = <1>;
274 		#size-cells = <1>;
278 			compatible = "rockchip,gpio-bank";
283 			gpio-controller;
284 			#gpio-cells = <2>;
286 			interrupt-controller;
287 			#interrupt-cells = <2>;
291 			compatible = "rockchip,gpio-bank";
296 			gpio-controller;
297 			#gpio-cells = <2>;
299 			interrupt-controller;
300 			#interrupt-cells = <2>;
304 			compatible = "rockchip,gpio-bank";
309 			gpio-controller;
310 			#gpio-cells = <2>;
312 			interrupt-controller;
313 			#interrupt-cells = <2>;
317 			compatible = "rockchip,gpio-bank";
322 			gpio-controller;
323 			#gpio-cells = <2>;
325 			interrupt-controller;
326 			#interrupt-cells = <2>;
330 			compatible = "rockchip,gpio-bank";
335 			gpio-controller;
336 			#gpio-cells = <2>;
338 			interrupt-controller;
339 			#interrupt-cells = <2>;
343 			compatible = "rockchip,gpio-bank";
348 			gpio-controller;
349 			#gpio-cells = <2>;
351 			interrupt-controller;
352 			#interrupt-cells = <2>;
355 		pcfg_pull_default: pcfg-pull-default {
356 			bias-pull-pin-default;
359 		pcfg_pull_none: pcfg-pull-none {
360 			bias-disable;
364 			emac_xfer: emac-xfer {
365 				rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
375 			emac_mdio: emac-mdio {
376 				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
382 			emmc_clk: emmc-clk {
383 				rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
386 			emmc_cmd: emmc-cmd {
387 				rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
390 			emmc_rst: emmc-rst {
391 				rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
395 			 * The data pins are shared between nandc and emmc and
398 			 * flash/emmc is the boot-device.
403 			hdmi_hpd: hdmi-hpd {
404 				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
407 			hdmii2c_xfer: hdmii2c-xfer {
408 				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
414 			i2c0_xfer: i2c0-xfer {
415 				rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
421 			i2c1_xfer: i2c1-xfer {
422 				rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
428 			i2c2_xfer: i2c2-xfer {
429 				rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
435 			i2c3_xfer: i2c3-xfer {
436 				rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
442 			i2c4_xfer: i2c4-xfer {
443 				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
449 			pwm0_out: pwm0-out {
450 				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
455 			pwm1_out: pwm1-out {
456 				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
461 			pwm2_out: pwm2-out {
462 				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
467 			pwm3_out: pwm3-out {
468 				rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
473 			spi0_clk: spi0-clk {
474 				rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
476 			spi0_cs0: spi0-cs0 {
477 				rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
479 			spi0_tx: spi0-tx {
480 				rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
482 			spi0_rx: spi0-rx {
483 				rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
485 			spi0_cs1: spi0-cs1 {
486 				rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
491 			spi1_clk: spi1-clk {
492 				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
494 			spi1_cs0: spi1-cs0 {
495 				rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
497 			spi1_rx: spi1-rx {
498 				rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
500 			spi1_tx: spi1-tx {
501 				rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
503 			spi1_cs1: spi1-cs1 {
504 				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
509 			uart0_xfer: uart0-xfer {
510 				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
514 			uart0_cts: uart0-cts {
515 				rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
518 			uart0_rts: uart0-rts {
519 				rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
524 			uart1_xfer: uart1-xfer {
525 				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
529 			uart1_cts: uart1-cts {
530 				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
533 			uart1_rts: uart1-rts {
534 				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
539 			uart2_xfer: uart2-xfer {
540 				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
547 			uart3_xfer: uart3-xfer {
548 				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
552 			uart3_cts: uart3-cts {
553 				rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
556 			uart3_rts: uart3-rts {
557 				rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
561 		sd0 {
562 			sd0_clk: sd0-clk {
563 				rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
566 			sd0_cmd: sd0-cmd {
567 				rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
570 			sd0_cd: sd0-cd {
571 				rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
574 			sd0_wp: sd0-wp {
575 				rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
578 			sd0_bus1: sd0-bus-width1 {
579 				rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
582 			sd0_bus4: sd0-bus-width4 {
583 				rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
591 			sd1_clk: sd1-clk {
592 				rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
595 			sd1_cmd: sd1-cmd {
596 				rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
599 			sd1_cd: sd1-cd {
600 				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
603 			sd1_wp: sd1-wp {
604 				rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
607 			sd1_bus1: sd1-bus-width1 {
608 				rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
611 			sd1_bus4: sd1-bus-width4 {
612 				rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
620 			i2s0_bus: i2s0-bus {
621 				rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
634 			i2s1_bus: i2s1-bus {
635 				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
645 			i2s2_bus: i2s2-bus {
646 				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
658 	compatible = "rockchip,rk3066-mali", "arm,mali-400";
669 	interrupt-names = "gp",
679 	power-domains = <&power RK3066_PD_GPU>;
683 	compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
686 		compatible = "rockchip,rk3066a-usb-phy";
687 		#address-cells = <1>;
688 		#size-cells = <0>;
691 		usbphy0: usb-phy@17c {
694 			clock-names = "phyclk";
695 			#clock-cells = <0>;
696 			#phy-cells = <0>;
699 		usbphy1: usb-phy@188 {
702 			clock-names = "phyclk";
703 			#clock-cells = <0>;
704 			#phy-cells = <0>;
710 	pinctrl-names = "default";
711 	pinctrl-0 = <&i2c0_xfer>;
715 	pinctrl-names = "default";
716 	pinctrl-0 = <&i2c1_xfer>;
720 	pinctrl-names = "default";
721 	pinctrl-0 = <&i2c2_xfer>;
725 	pinctrl-names = "default";
726 	pinctrl-0 = <&i2c3_xfer>;
730 	pinctrl-names = "default";
731 	pinctrl-0 = <&i2c4_xfer>;
735 	clock-frequency = <50000000>;
737 	dma-names = "rx-tx";
738 	max-frequency = <50000000>;
739 	pinctrl-names = "default";
740 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
745 	dma-names = "rx-tx";
746 	pinctrl-names = "default";
747 	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
752 	dma-names = "rx-tx";
756 	power: power-controller {
757 		compatible = "rockchip,rk3066-power-controller";
758 		#power-domain-cells = <1>;
759 		#address-cells = <1>;
760 		#size-cells = <0>;
762 		power-domain@RK3066_PD_VIO {
787 			#power-domain-cells = <0>;
790 		power-domain@RK3066_PD_VIDEO {
797 			#power-domain-cells = <0>;
800 		power-domain@RK3066_PD_GPU {
804 			#power-domain-cells = <0>;
810 	pinctrl-names = "default";
811 	pinctrl-0 = <&pwm0_out>;
815 	pinctrl-names = "default";
816 	pinctrl-0 = <&pwm1_out>;
820 	pinctrl-names = "default";
821 	pinctrl-0 = <&pwm2_out>;
825 	pinctrl-names = "default";
826 	pinctrl-0 = <&pwm3_out>;
830 	pinctrl-names = "default";
831 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
835 	pinctrl-names = "default";
836 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
840 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
842 	dma-names = "tx", "rx";
843 	pinctrl-names = "default";
844 	pinctrl-0 = <&uart0_xfer>;
848 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
850 	dma-names = "tx", "rx";
851 	pinctrl-names = "default";
852 	pinctrl-0 = <&uart1_xfer>;
856 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
858 	dma-names = "tx", "rx";
859 	pinctrl-names = "default";
860 	pinctrl-0 = <&uart2_xfer>;
864 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
866 	dma-names = "tx", "rx";
867 	pinctrl-names = "default";
868 	pinctrl-0 = <&uart3_xfer>;
872 	power-domains = <&power RK3066_PD_VIDEO>;
876 	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
880 	compatible = "rockchip,rk3066-emac";