Lines Matching +full:0 +full:xe6180000
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
149 reg = <0 0xe61c0200 0 0x200>;
182 reg = <0 0xe6050000 0 0x9000>;
186 <&pfc 0 0 31>, <&pfc 32 32 9>,
193 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
194 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
195 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
196 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
197 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
198 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
199 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
200 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
201 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
202 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
203 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
204 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
205 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
206 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
207 <&irqc1 24 0>, <&irqc1 25 0>;
213 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
214 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
222 #size-cells = <0>;
224 reg = <0 0xe6500000 0 0x428>;
233 #size-cells = <0>;
235 reg = <0 0xe6510000 0 0x428>;
244 #size-cells = <0>;
246 reg = <0 0xe6520000 0 0x428>;
255 #size-cells = <0>;
257 reg = <0 0xe6530000 0 0x428>;
266 #size-cells = <0>;
268 reg = <0 0xe6540000 0 0x428>;
277 #size-cells = <0>;
279 reg = <0 0xe6550000 0 0x428>;
288 #size-cells = <0>;
290 reg = <0 0xe6560000 0 0x428>;
299 #size-cells = <0>;
301 reg = <0 0xe6570000 0 0x428>;
310 reg = <0 0xe6c20000 0 0x100>;
320 reg = <0 0xe6c30000 0 0x100>;
330 reg = <0 0xe6c40000 0 0x100>;
340 reg = <0 0xe6c50000 0 0x100>;
350 reg = <0 0xe6ce0000 0 0x100>;
360 reg = <0 0xe6cf0000 0 0x100>;
370 reg = <0 0xee100000 0 0x100>;
380 reg = <0 0xee120000 0 0x100>;
390 reg = <0 0xee140000 0 0x100>;
400 reg = <0 0xee200000 0 0x80>;
410 reg = <0 0xee220000 0 0x80>;
421 #address-cells = <0>;
423 reg = <0 0xf1001000 0 0x1000>,
424 <0 0xf1002000 0 0x2000>,
425 <0 0xf1004000 0 0x2000>,
426 <0 0xf1006000 0 0x2000>;
438 ranges = <0 0 0 0x20000000>;
439 reg = <0 0xfec10000 0 0x400>;
452 #clock-cells = <0>;
454 clock-frequency = <0>;
458 #clock-cells = <0>;
460 clock-frequency = <0>;
464 #clock-cells = <0>;
466 clock-frequency = <0>;
470 #clock-cells = <0>;
472 clock-frequency = <0>;
476 #clock-cells = <0>;
478 clock-frequency = <0>;
484 reg = <0 0xe6150000 0 0x10000>;
496 reg = <0 0xe6150010 0 4>;
497 clocks = <&pll1_div2_clk>, <0>,
498 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
499 #clock-cells = <0>;
504 reg = <0 0xe6150074 0 4>;
506 <0>, <&extal2_clk>;
507 #clock-cells = <0>;
511 reg = <0 0xe6150078 0 4>;
513 <0>, <&extal2_clk>;
514 #clock-cells = <0>;
518 reg = <0 0xe615007c 0 4>;
520 <0>, <&extal2_clk>;
521 #clock-cells = <0>;
525 reg = <0 0xe6150240 0 4>;
527 <0>, <&extal2_clk>;
528 #clock-cells = <0>;
532 reg = <0 0xe6150244 0 4>;
534 <0>, <&extal2_clk>;
535 #clock-cells = <0>;
539 reg = <0 0xe6150008 0 4>;
541 <0>, <&extal2_clk>, <&main_div2_clk>,
542 <&extalr_clk>, <0>, <0>;
543 #clock-cells = <0>;
547 reg = <0 0xe615000c 0 4>;
549 <0>, <&extal2_clk>, <&main_div2_clk>,
550 <&extalr_clk>, <0>, <0>;
551 #clock-cells = <0>;
555 reg = <0 0xe615001c 0 4>;
557 <0>, <&extal2_clk>, <&main_div2_clk>,
558 <&extalr_clk>, <0>, <0>;
559 #clock-cells = <0>;
563 reg = <0 0xe6150014 0 4>;
565 <0>, <&extal2_clk>, <&main_div2_clk>,
566 <&extalr_clk>, <0>, <0>;
567 #clock-cells = <0>;
571 reg = <0 0xe6150034 0 4>;
573 <0>, <&extal2_clk>, <&main_div2_clk>,
574 <&extalr_clk>, <0>, <0>;
575 #clock-cells = <0>;
579 reg = <0 0xe6150018 0 4>;
581 <&fsiack_clk>, <0>;
582 #clock-cells = <0>;
586 reg = <0 0xe6150090 0 4>;
588 <&fsibck_clk>, <0>;
589 #clock-cells = <0>;
593 reg = <0 0xe6150080 0 4>;
596 #clock-cells = <0>;
600 reg = <0 0xe6150098 0 4>;
602 #clock-cells = <0>;
606 reg = <0 0xe615026c 0 4>;
608 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
609 #clock-cells = <0>;
613 reg = <0 0xe6150094 0 4>;
616 #clock-cells = <0>;
623 #clock-cells = <0>;
630 #clock-cells = <0>;
637 #clock-cells = <0>;
644 #clock-cells = <0>;
652 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
668 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
691 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
707 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
720 reg = <0 0xff000044 0 4>;
725 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
730 #size-cells = <0>;
731 #power-domain-cells = <0>;
733 pd_c4: c4@0 {
734 reg = <0>;
736 #size-cells = <0>;
737 #power-domain-cells = <0>;
741 #power-domain-cells = <0>;
746 #power-domain-cells = <0>;
752 #size-cells = <0>;
753 #power-domain-cells = <0>;
757 #power-domain-cells = <0>;
764 #size-cells = <0>;
765 #power-domain-cells = <0>;
769 #power-domain-cells = <0>;
776 #size-cells = <0>;
777 #power-domain-cells = <0>;
781 #power-domain-cells = <0>;
788 #power-domain-cells = <0>;
793 #power-domain-cells = <0>;
798 #power-domain-cells = <0>;
804 #size-cells = <0>;
805 #power-domain-cells = <0>;
809 #power-domain-cells = <0>;
815 #power-domain-cells = <0>;
820 #power-domain-cells = <0>;
826 #size-cells = <0>;
827 #power-domain-cells = <0>;
831 #power-domain-cells = <0>;
836 #power-domain-cells = <0>;
842 #power-domain-cells = <0>;
848 #size-cells = <0>;
849 #power-domain-cells = <0>;
853 #power-domain-cells = <0>;
858 #power-domain-cells = <0>;