Lines Matching +full:r7s72100 +full:- +full:ostm
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the r7s72100 SoC
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "renesas,r7s72100";
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
35 clock-mult = <1>;
36 clock-div = <3>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a9";
47 clock-frequency = <400000000>;
49 next-level-cache = <&L2>;
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
58 clock-frequency = <0>;
62 #clock-cells = <0>;
63 compatible = "fixed-factor-clock";
65 clock-mult = <1>;
66 clock-div = <12>;
70 #clock-cells = <0>;
71 compatible = "fixed-factor-clock";
73 clock-mult = <1>;
74 clock-div = <6>;
78 compatible = "arm,cortex-a9-pmu";
79 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
86 clock-frequency = <0>;
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
93 clock-frequency = <0>;
97 compatible = "simple-bus";
98 interrupt-parent = <&gic>;
100 #address-cells = <1>;
101 #size-cells = <1>;
104 L2: cache-controller@3ffff000 {
105 compatible = "arm,pl310-cache";
108 arm,early-bresp-disable;
109 arm,full-line-zero-disable;
110 cache-unified;
111 cache-level = <2>;
115 compatible = "renesas,scif-r7s72100", "renesas,scif";
122 clock-names = "fck";
123 power-domains = <&cpg_clocks>;
128 compatible = "renesas,scif-r7s72100", "renesas,scif";
135 clock-names = "fck";
136 power-domains = <&cpg_clocks>;
141 compatible = "renesas,scif-r7s72100", "renesas,scif";
148 clock-names = "fck";
149 power-domains = <&cpg_clocks>;
154 compatible = "renesas,scif-r7s72100", "renesas,scif";
161 clock-names = "fck";
162 power-domains = <&cpg_clocks>;
167 compatible = "renesas,scif-r7s72100", "renesas,scif";
174 clock-names = "fck";
175 power-domains = <&cpg_clocks>;
180 compatible = "renesas,scif-r7s72100", "renesas,scif";
187 clock-names = "fck";
188 power-domains = <&cpg_clocks>;
193 compatible = "renesas,scif-r7s72100", "renesas,scif";
200 clock-names = "fck";
201 power-domains = <&cpg_clocks>;
206 compatible = "renesas,scif-r7s72100", "renesas,scif";
213 clock-names = "fck";
214 power-domains = <&cpg_clocks>;
219 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
224 interrupt-names = "error", "rx", "tx";
226 power-domains = <&cpg_clocks>;
227 num-cs = <1>;
228 #address-cells = <1>;
229 #size-cells = <0>;
234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
239 interrupt-names = "error", "rx", "tx";
241 power-domains = <&cpg_clocks>;
242 num-cs = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
249 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
254 interrupt-names = "error", "rx", "tx";
256 power-domains = <&cpg_clocks>;
257 num-cs = <1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
264 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
269 interrupt-names = "error", "rx", "tx";
271 power-domains = <&cpg_clocks>;
272 num-cs = <1>;
273 #address-cells = <1>;
274 #size-cells = <0>;
279 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
284 interrupt-names = "error", "rx", "tx";
286 power-domains = <&cpg_clocks>;
287 num-cs = <1>;
288 #address-cells = <1>;
289 #size-cells = <0>;
294 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
299 power-domains = <&cpg_clocks>;
304 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
309 power-domains = <&cpg_clocks>;
314 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
320 power-domains = <&cpg_clocks>;
321 reg-io-width = <4>;
322 bus-width = <8>;
327 compatible = "renesas,sdhi-r7s72100";
335 clock-names = "core", "cd";
336 power-domains = <&cpg_clocks>;
337 cap-sd-highspeed;
338 cap-sdio-irq;
343 compatible = "renesas,sdhi-r7s72100";
351 clock-names = "core", "cd";
352 power-domains = <&cpg_clocks>;
353 cap-sd-highspeed;
354 cap-sdio-irq;
358 gic: interrupt-controller@e8201000 {
360 #interrupt-cells = <3>;
361 #address-cells = <0>;
362 interrupt-controller;
368 compatible = "renesas,ether-r7s72100";
373 power-domains = <&cpg_clocks>;
374 phy-mode = "mii";
375 #address-cells = <1>;
376 #size-cells = <0>;
382 compatible = "renesas,r7s72100-ceu";
385 power-domains = <&cpg_clocks>;
390 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
398 #clock-cells = <1>;
399 compatible = "renesas,r7s72100-cpg-clocks",
400 "renesas,rz-cpg-clocks";
403 clock-output-names = "pll", "i", "g";
404 #power-domain-cells = <0>;
409 #clock-cells = <1>;
410 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
413 clock-indices = <R7S72100_CLK_MTU2>;
414 clock-output-names = "mtu2";
418 #clock-cells = <1>;
419 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
423 clock-indices = <
427 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
431 #clock-cells = <1>;
432 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
435 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
436 clock-output-names = "ostm0", "ostm1";
440 #clock-cells = <1>;
441 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
444 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
445 clock-output-names = "ceu", "rtc";
449 #clock-cells = <1>;
450 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
453 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
454 clock-output-names = "ether", "usb0", "usb1";
458 #clock-cells = <1>;
459 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
462 clock-indices = <R7S72100_CLK_MMCIF>;
463 clock-output-names = "mmcif";
467 #clock-cells = <1>;
468 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
471 clock-indices = <
475 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
479 #clock-cells = <1>;
480 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
484 clock-indices = <
488 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
491 #clock-cells = <1>;
492 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
495 clock-indices = <
499 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
503 compatible = "renesas,r7s72100-ports";
507 port0: gpio-0 {
508 gpio-controller;
509 #gpio-cells = <2>;
510 gpio-ranges = <&pinctrl 0 0 6>;
513 port1: gpio-1 {
514 gpio-controller;
515 #gpio-cells = <2>;
516 gpio-ranges = <&pinctrl 0 16 16>;
519 port2: gpio-2 {
520 gpio-controller;
521 #gpio-cells = <2>;
522 gpio-ranges = <&pinctrl 0 32 16>;
525 port3: gpio-3 {
526 gpio-controller;
527 #gpio-cells = <2>;
528 gpio-ranges = <&pinctrl 0 48 16>;
531 port4: gpio-4 {
532 gpio-controller;
533 #gpio-cells = <2>;
534 gpio-ranges = <&pinctrl 0 64 16>;
537 port5: gpio-5 {
538 gpio-controller;
539 #gpio-cells = <2>;
540 gpio-ranges = <&pinctrl 0 80 11>;
543 port6: gpio-6 {
544 gpio-controller;
545 #gpio-cells = <2>;
546 gpio-ranges = <&pinctrl 0 96 16>;
549 port7: gpio-7 {
550 gpio-controller;
551 #gpio-cells = <2>;
552 gpio-ranges = <&pinctrl 0 112 16>;
555 port8: gpio-8 {
556 gpio-controller;
557 #gpio-cells = <2>;
558 gpio-ranges = <&pinctrl 0 128 16>;
561 port9: gpio-9 {
562 gpio-controller;
563 #gpio-cells = <2>;
564 gpio-ranges = <&pinctrl 0 144 8>;
567 port10: gpio-10 {
568 gpio-controller;
569 #gpio-cells = <2>;
570 gpio-ranges = <&pinctrl 0 160 16>;
573 port11: gpio-11 {
574 gpio-controller;
575 #gpio-cells = <2>;
576 gpio-ranges = <&pinctrl 0 176 16>;
581 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
585 power-domains = <&cpg_clocks>;
590 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
594 power-domains = <&cpg_clocks>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
611 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 clock-frequency = <100000>;
615 power-domains = <&cpg_clocks>;
620 #address-cells = <1>;
621 #size-cells = <0>;
622 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
632 interrupt-names = "tei", "ri", "ti", "spi", "sti",
635 clock-frequency = <100000>;
636 power-domains = <&cpg_clocks>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
653 interrupt-names = "tei", "ri", "ti", "spi", "sti",
656 clock-frequency = <100000>;
657 power-domains = <&cpg_clocks>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
674 interrupt-names = "tei", "ri", "ti", "spi", "sti",
677 clock-frequency = <100000>;
678 power-domains = <&cpg_clocks>;
682 irqc: interrupt-controller@fcfef800 {
683 compatible = "renesas,r7s72100-irqc",
684 "renesas,rza1-irqc";
685 #interrupt-cells = <2>;
686 #address-cells = <0>;
687 interrupt-controller;
689 interrupt-map =
698 interrupt-map-mask = <7 0>;
702 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
705 interrupt-names = "tgi0a";
707 clock-names = "fck";
708 power-domains = <&cpg_clocks>;
713 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
718 interrupt-names = "alarm", "period", "carry";
721 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
722 power-domains = <&cpg_clocks>;
728 #clock-cells = <0>;
729 compatible = "fixed-clock";
731 clock-frequency = <0>;