Lines Matching +full:smp2p +full:- +full:modem
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
21 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 clock-output-names = "xo_board";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
40 #clock-cells = <0>;
43 nand_clk_dummy: nand-clk-dummy {
44 compatible = "fixed-clock";
45 clock-frequency = <32764>;
46 #clock-cells = <0>;
51 #address-cells = <1>;
52 #size-cells = <0>;
56 compatible = "arm,cortex-a7";
58 enable-method = "psci";
60 power-domains = <&rpmhpd SDX65_CX_AO>;
61 power-domain-names = "rpmhpd";
62 operating-points-v2 = <&cpu_opp_table>;
68 compatible = "qcom,scm-sdx65", "qcom,scm";
72 mc_virt: interconnect-mc-virt {
73 compatible = "qcom,sdx65-mc-virt";
74 #interconnect-cells = <1>;
75 qcom,bcm-voters = <&apps_bcm_voter>;
78 cpu_opp_table: opp-table-cpu {
79 compatible = "operating-points-v2";
80 opp-shared;
82 opp-345600000 {
83 opp-hz = /bits/ 64 <345600000>;
84 required-opps = <&rpmhpd_opp_low_svs>;
87 opp-576000000 {
88 opp-hz = /bits/ 64 <576000000>;
89 required-opps = <&rpmhpd_opp_svs>;
92 opp-1094400000 {
93 opp-hz = /bits/ 64 <1094400000>;
94 required-opps = <&rpmhpd_opp_nom>;
97 opp-1497600000 {
98 opp-hz = /bits/ 64 <1497600000>;
99 required-opps = <&rpmhpd_opp_turbo>;
104 compatible = "arm,psci-1.0";
108 reserved_memory: reserved-memory {
109 #address-cells = <1>;
110 #size-cells = <1>;
114 no-map;
119 no-map;
124 no-map;
129 no-map;
134 no-map;
142 no-map;
145 cmd_db: reserved-memory@8fee0000 {
146 compatible = "qcom,cmd-db";
148 no-map;
152 no-map;
157 no-map;
162 no-map;
167 smp2p-mpss {
168 compatible = "qcom,smp2p";
172 qcom,local-pid = <0>;
173 qcom,remote-pid = <1>;
175 modem_smp2p_out: master-kernel {
176 qcom,entry-name = "master-kernel";
177 #qcom,smem-state-cells = <1>;
180 modem_smp2p_in: slave-kernel {
181 qcom,entry-name = "slave-kernel";
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 ipa_smp2p_out: ipa-ap-to-modem {
187 qcom,entry-name = "ipa";
188 #qcom,smem-state-cells = <1>;
191 ipa_smp2p_in: ipa-modem-to-ap {
192 qcom,entry-name = "ipa";
193 interrupt-controller;
194 #interrupt-cells = <2>;
199 #address-cells = <1>;
200 #size-cells = <1>;
202 compatible = "simple-bus";
204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc-sdx65";
208 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
209 #power-domain-cells = <1>;
210 #clock-cells = <1>;
211 #reset-cells = <1>;
215 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
219 clock-names = "core", "iface";
224 compatible = "qcom,sdx65-usb-hs-phy",
225 "qcom,usb-snps-hs-7nm-phy";
227 #phy-cells = <0>;
229 clock-names = "ref";
235 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
237 #address-cells = <1>;
238 #size-cells = <1>;
244 clock-names = "aux", "cfg_ahb", "ref";
248 reset-names = "phy", "common";
256 #phy-cells = <0>;
257 #clock-cells = <0>;
259 clock-names = "pipe0";
260 clock-output-names = "usb3_uni_phy_pipe_clk_src";
265 compatible = "qcom,sdx65-system-noc";
267 #interconnect-cells = <1>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
271 qpic_bam: dma-controller@1b04000 {
272 compatible = "qcom,bam-v1.7.0";
276 clock-names = "bam_clk";
277 #dma-cells = <1>;
279 qcom,controlled-remotely;
283 qpic_nand: nand-controller@1b30000 {
284 compatible = "qcom,sdx55-nand";
286 #address-cells = <1>;
287 #size-cells = <0>;
290 clock-names = "core", "aon";
295 dma-names = "tx", "rx", "cmd";
299 pcie_ep: pcie-ep@1c00000 {
300 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
307 reg-names = "parf",
314 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
323 clock-names = "aux",
333 interrupt-names = "global", "doorbell";
336 reset-names = "core";
338 power-domains = <&gcc PCIE_GDSC>;
341 phy-names = "pciephy";
343 max-link-speed = <3>;
344 num-lanes = <2>;
350 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
358 clock-names = "aux",
365 reset-names = "phy";
367 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
368 assigned-clock-rates = <100000000>;
370 power-domains = <&gcc PCIE_GDSC>;
372 #clock-cells = <0>;
373 clock-output-names = "pcie_pipe_clk";
375 #phy-cells = <0>;
381 compatible = "qcom,tcsr-mutex";
383 #hwlock-cells = <1>;
387 compatible = "qcom,sdx65-tcsr", "syscon";
392 compatible = "qcom,sdx65-ipa";
397 reg-names = "ipa-reg",
398 "ipa-shared",
401 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
405 interrupt-names = "ipa",
407 "ipa-clock-query",
408 "ipa-setup-ready";
414 clock-names = "core";
418 interconnect-names = "memory",
421 qcom,smem-states = <&ipa_smp2p_out 0>,
423 qcom,smem-state-names = "ipa-clock-enabled-valid",
424 "ipa-clock-enabled";
430 compatible = "qcom,sdx55-mpss-pas";
433 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
439 interrupt-names = "wdog", "fatal", "ready", "handover",
440 "stop-ack", "shutdown-ack";
443 clock-names = "xo";
445 power-domains = <&rpmhpd SDX65_CX>,
447 power-domain-names = "cx", "mss";
449 qcom,smem-states = <&modem_smp2p_out 0>;
450 qcom,smem-state-names = "stop";
454 glink-edge {
457 qcom,remote-pid = <1>;
463 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
465 reg-names = "hc";
468 interrupt-names = "hc_irq", "pwr_irq";
471 clock-names = "core", "iface";
476 compatible = "qcom,sdx65-mem-noc";
478 #interconnect-cells = <1>;
479 qcom,bcm-voters = <&apps_bcm_voter>;
483 compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
485 #address-cells = <1>;
486 #size-cells = <1>;
494 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
497 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
499 assigned-clock-rates = <19200000>, <200000000>;
501 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
505 interrupt-names = "hs_phy_irq",
510 power-domains = <&gcc USB30_GDSC>;
524 phy-names = "usb2-phy", "usb3-phy";
534 compatible = "qcom,spmi-pmic-arb";
540 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
541 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "periph_irq";
543 interrupt-controller;
544 #interrupt-cells = <4>;
545 #address-cells = <2>;
546 #size-cells = <0>;
547 cell-index = <0>;
553 compatible = "qcom,sdx65-tlmm";
556 gpio-controller;
557 #gpio-cells = <2>;
558 gpio-ranges = <&tlmm 0 0 109>;
559 interrupt-controller;
560 interrupt-parent = <&intc>;
561 #interrupt-cells = <2>;
564 pdc: interrupt-controller@b210000 {
565 compatible = "qcom,sdx65-pdc", "qcom,pdc";
567 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
568 #interrupt-cells = <2>;
569 interrupt-parent = <&intc>;
570 interrupt-controller;
574 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
577 #address-cells = <1>;
578 #size-cells = <1>;
580 pil-reloc@94c {
581 compatible = "qcom,pil-reloc-info";
587 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
589 #iommu-cells = <2>;
590 #global-interrupts = <1>;
626 intc: interrupt-controller@17800000 {
627 compatible = "qcom,msm-qgic2";
628 interrupt-controller;
629 interrupt-parent = <&intc>;
630 #interrupt-cells = <3>;
636 compatible = "qcom,sdx55-a7pll";
639 clock-names = "bi_tcxo";
640 #clock-cells = <0>;
644 compatible = "qcom,sdx55-apcs-gcc", "syscon";
646 #mbox-cells = <1>;
648 clock-names = "ref", "pll", "aux";
649 #clock-cells = <0>;
653 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
659 #address-cells = <1>;
660 #size-cells = <1>;
662 compatible = "arm,armv7-timer-mem";
664 clock-frequency = <19200000>;
667 frame-number = <0>;
675 frame-number = <1>;
682 frame-number = <2>;
689 frame-number = <3>;
696 frame-number = <4>;
703 frame-number = <5>;
710 frame-number = <6>;
717 frame-number = <7>;
726 compatible = "qcom,rpmh-rsc";
729 reg-names = "drv-0", "drv-1";
732 qcom,tcs-offset = <0xd00>;
733 qcom,drv-id = <1>;
734 qcom,tcs-config = <ACTIVE_TCS 2>,
739 rpmhcc: clock-controller {
740 compatible = "qcom,sdx65-rpmh-clk";
741 #clock-cells = <1>;
742 clock-names = "xo";
746 rpmhpd: power-controller {
747 compatible = "qcom,sdx65-rpmhpd";
748 #power-domain-cells = <1>;
749 operating-points-v2 = <&rpmhpd_opp_table>;
751 rpmhpd_opp_table: opp-table {
752 compatible = "operating-points-v2";
755 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
759 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
763 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
767 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
775 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
779 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
787 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
796 apps_bcm_voter: bcm-voter {
797 compatible = "qcom,bcm-voter";
804 compatible = "arm,armv7-timer";
809 clock-frequency = <19200000>;